Design techniques for fault-tolerant systolic arrays

  • M. O. Esonu
  • A. J. Al-Khalili
  • S. Hariri
  • D. Al-Khalili


A systematic approach of designing fault-tolerant systolic architectures is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of the three versions of the algorithm. The merging method attempts to obtain the fault-tolerant systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect and tolerate all single permanent and temporary faults and the majority of the multiple fault patterns with high probability.


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  1. 1.
    H.T. Kung, “Why Systolic Architectures?”IEEE Computer, Vol. 15, pp. 37–46, 1982.CrossRefGoogle Scholar
  2. 2.
    J.-M. Delosme and I.C.F. Ispen, “Efficient systolic arrays for the solution of Toeplitz systems: An illustration of a methodology for the construction of systolic architectures in VLSI,”International Workshop on Systolic Arrays, University of Oxford, p. F2, July, 1986. Also inSystolic Arrays, W. Moore, A. McCabe, and R. Urquhart (Eds.), Bristol-Hilger, pp. 27–46, 1987.Google Scholar
  3. 3.
    A.L. DeCegama, “The Technology of Parallel Processing”Parallel Processing Architectures and VLSI Hardware, Vol. I, Prentice Hall, Englewood Cliffs, New Jersey, 1989.Google Scholar
  4. 4.
    S.Y. Kung,VLSI Array Processors, Prentice-Hall, 1988.Google Scholar
  5. 5.
    H.T. Kung and M.S. Lam, “Fault-Tolerance and Two Level Pipelining in VLSI Systolic Arrays,”MIT Conference on Advanced Research in VLSI, pp. 74–83, Jan. 1984.Google Scholar
  6. 6.
    J.-H. Kim and S.M. Reddy, “On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement,”IEEE Trans. Comput., Vol. 38, pp. 515–525, 1989.CrossRefGoogle Scholar
  7. 7.
    F.T. Leighton and C.E. Leiserson, “Wafer-Scale Integration of Systolic Arrays,”IEEE Trans. Computers, Vol. C-34, pp. 448–461, 1985.CrossRefGoogle Scholar
  8. 8.
    P.J. Varman and I.V. Ramakrishnan, “Optimal matrix multiplication on fault-tolerant VLSI array,”IEEE Trans. Comput., Vol. 38, pp. 278–283, 1989.MathSciNetCrossRefMATHGoogle Scholar
  9. 9.
    V.K. Prasanna Kumar and Y.-C. Tsai, “On mapping Algorithm to Linear and Fault-Tolerant Systolic Arrays,”IEEE Trans. Comput., Vol. 38, pp. 470–480, 1989.MathSciNetCrossRefGoogle Scholar
  10. 10.
    J-H Kim and S.M. Reddy, “A Fault-Tolerant Systolic Array Design using TMR Method,”1985 ICCD, pp. 769–773.Google Scholar
  11. 11.
    J.V. Neuman, “Probabilistic Logics and Synthesis of Reliable Organisms from Unreliable Components,”Automata Studies, No. 34, pp. 43–99, Princeton, NJ: Princeton University Press.Google Scholar
  12. 12.
    R.J. Cosentino, “Fault Tolerance in a Systolic Residue Arithmetic Processor Array,”IEEE Trans. on Comput., Vol. 37, pp. 886–890, 1988.CrossRefGoogle Scholar
  13. 13.
    S.-W. Chan and C.-L. Wey, “The Design of Concurrent Error Diagnosable Systolic Arrays for Band Matrix Multiplication,”Proc. IEEE Trans. on Computer-Aided Design, Vol. 7, pp. 21–37, 1988.CrossRefGoogle Scholar
  14. 14.
    R.J. Cosentino, “Concurrent Error Correction in Systolic Architectures,”Proc. IEEE Trans. on Computer-Aided Design, Vol. 7, pp. 117–125, 1988.CrossRefGoogle Scholar
  15. 15.
    E.S. Manolakos, “Transient Fault Recovery Techniques for the VLSI Processor Arrays,” Ph.D. Thesis, University of Southern California, May 1989.Google Scholar
  16. 16.
    K.-H. Huang and J.A. Abraham, “Low Cost Schemes for Fault Tolerance in Matrix Operations with Processor Arrays,”Proc. 9th Symp. on Computer Architecture, pp. 330–337, May 1982.Google Scholar
  17. 17.
    K.-H. Huang and J.A. Abraham, “Fault-Tolerant Algorithms and their Application to Solving Laplace Equations,”IEEE Int'l Conf. Parallel Processing, pp. 117–122, Aug. 1984.Google Scholar
  18. 18.
    K.-H. Huang and J.A. Abraham, “Algorithm-Based Fault Tolerance for Matrix Operations,”IEEE Trans. on Comput., Vol. C-33, pp. 518–528, 1984.CrossRefGoogle Scholar
  19. 19.
    J.-Y. Jou and J.A. Abraham, “Fault-Tolerant Matrix Arithmetic and Signal Processing on Highly Concurrent Computing Structures,”Proceedings of the IEEE, Vol. 74, pp. 732–741, 1986.CrossRefGoogle Scholar
  20. 20.
    J.A. Abraham, P. Banerjee, C.-Y. Chen, W.K. Fuchs, S.-Y. Kuo, and N. Reddy, “Fault-Tolerance techniques for systolic arrays,”IEEE Computer, pp. 65–74, 1987.Google Scholar
  21. 21.
    H. Lev-Ari and B. Friedlander, “On the Systematic Design of Fault-Tolerant Processor Arrays with Application to Digital Filtering,”1988 VLSI Signal Processing III, pp. 483–494, 1988.Google Scholar
  22. 22.
    C.J. Anfinson and F.T. Luk, “A Linear Algebraic Model of Algorithm-Based Fault-Tolerance,”IEEE Trans. Comput., Vol. 37, pp. 1599–1604, 1988.MathSciNetCrossRefMATHGoogle Scholar
  23. 23.
    D.L. Boley and F.T. Luk, “A Well Conditioned Checksum Scheme for Algorithmic Fault-Tolerance,”Integration, The VLSI Journal, Vol.12, pp. 21–32, 1991.CrossRefGoogle Scholar
  24. 24.
    W. Shang and J.A.B. Fortes, “On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays,”IEEE Trans. on Parallel Distributed Syst., Vol. 3, pp. 350–363, 1992.CrossRefGoogle Scholar
  25. 25.
    P. Cappello, “A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms,”IEEE Trans. on Parallel and Distributed Syst., Vol. 3, pp. 4–13, 1992.CrossRefGoogle Scholar
  26. 26.
    J.-P. Sheu and C.-Y. Chang, “Synthesizing Nested Loop Algorithms Using Nonlinear Transformation Method,”IEEE Trans. on Parallel Distributed Syst., Vol. 2, pp. 304–317, 1991.CrossRefGoogle Scholar
  27. 27.
    D.I. Moldovan and J.A.B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays,”IEEE Trans. Comput., Vol. C-35, pp. 1–12, 1986.CrossRefGoogle Scholar
  28. 28.
    W.L. Miranker and A. Winkler, “Spacetime Representations of Computational Structures,”Journal of Computing, Vol. 32, pp. 93–114, 1984.MathSciNetCrossRefMATHGoogle Scholar
  29. 29.
    M.O. Esonu, S. Hariri, and A.J. Al-Khalili, “A Systematic Approach for Mapping Algorithms into Optimal Systolic Architectures,”IEEE Symp. on Parallel and Distributed Processing, Dallas Texas, Dec. 9–13, 1990, pp. 166–173.Google Scholar
  30. 30.
    M.O. Esonu, A.J. Al-Khalili, S. Hariri, and D. Al-Khalili, “Systolic Arrays: How to Choose Them,”IEE Proceedings-E, Computers and Digital Techniques, Vol. 139, pp. 179–188, 1992.CrossRefGoogle Scholar
  31. 31.
    H.F. Li, C.N. Zhang, and R. Jayakumar, “Latency of Computational Data Flow and Concurrent Error Detection in Systolic Arrays,”CCVLSI '89, pp. 251–258, 1989.Google Scholar
  32. 32.
    M.O. Esonu, A.J. Al-Khalili, and S. Hariri, “Area Efficient Architectures for Concurrent Error Detection in Systolic Arrays,”IEEE Int'l Conf. on Parallel Processing (ICPP '91), St. Charles, IL., 1991, pp. 1484–1491.Google Scholar
  33. 33.
    M.O. Esonu, A.J. Al-Khalili, and S. Hariri, “Fault-Tolerant Computing Structures for Systolic Arrays,”Int'l Symp. on Mini and Micro-computers (ISMM), Pittsburgh, Oct. 1992, pp. 40–45.Google Scholar
  34. 34.
    L. Chen and A. Avizienis, “N-version Programming: A Faulttolerant Approach to Reliability of Software Operation,”Proc. Int. Symp. Fault-tolerant Computing, pp. 3–9, 1978.Google Scholar
  35. 35.
    H. Hecht, “Fault-tolerant software,”IEEE Trans. Reliability, pp. 227–232, Aug. 1979.Google Scholar

Copyright information

© Kluwer Academic Publishers 1995

Authors and Affiliations

  • M. O. Esonu
    • 1
  • A. J. Al-Khalili
    • 1
  • S. Hariri
    • 2
  • D. Al-Khalili
    • 3
  1. 1.Department of Electrical and Computer EngineeringConcordia UniversityMontrealCanada
  2. 2.Electrical and Computer Engineering DepartmentSyracuse UniversitySyracuseUSA
  3. 3.ECE Dept.Royal Military CollegeKingstonCanada

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