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BIT Numerical Mathematics

, Volume 27, Issue 4, pp 480–500 | Cite as

Verification of a class of self-timed computational networks

  • Rami Melhem
Part I Computer Science

Abstract

A mathematical model for systolic networks is generalized and applied to a class of VLSI cellular networks which is defined to include both systolic and self-timed networks. The general model is kept simple by assuming that a computation does not deadlock, that is by separating the verification of liveness from the the verification of the results. The main contribution of this paper concerns the study of deadlock in self-timed computational networks. More specifically, an algebra of events is developed and used to prove that the liveness of any self-timed network is determined uniquely by its initial state. Moreover, a method is presented for the verification of liveness in networks preset to given initial states.

CR Categories

B.6.1 B.6.3 C.1.2 

Keywords

Data Driven Networks Systolic Networks Computational Arrays Abstract Model Formal Verification Deadlock Liveness Algebra of Events 

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Copyright information

© BIT Foundations 1987

Authors and Affiliations

  • Rami Melhem
    • 1
  1. 1.Department of Computer ScienceThe University of PittsburghPittsburghUSA

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