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BIT Numerical Mathematics

, Volume 10, Issue 2, pp 125–144 | Cite as

A flow-mode, self-steering, cellular multiplier-summation processor

  • Dines Bjørner
Article
  • 17 Downloads

Abstract

Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.

Keywords

Cellular Logic Iterative Array Vector Processing Flow Mode Self-Steering Asynchronous Control Arithmetic 

CR categories

6.1 6.32 6.33 

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Bibliography & References

  1. 1.
    S. Winograd,On the time required to perform addition, J. ACM., Vol. 12, No. 2, April 1965, pp. 277–285.Google Scholar
  2. 2.
    S. Winograd,On the time required to perform multiplication, J. ACM., Vol. 14, No. 4, October 1967, pp. 793–802.Google Scholar
  3. 3.
    N. S. Szabo, R. I. Tanaka,Residue Arithmetic and its applications to Computer Technology, McGraw-Hill, New York, N.Y., 1967.Google Scholar
  4. 4.
    A. Avizienis,Signed digit number representations for fast parallel arithmetic, IRE Trans. on Electronic Computers, Vol. EC-10, No. 3, Sept. 1961, pp. 389–400.Google Scholar
  5. 5.
    C. Y. Lee, M. C. Paull,A content-addressable distributed logic memory with applications to Information retrieval, Proc. IEEE, Vol. 51, June 1963, pp. 924–932.Google Scholar
  6. 6.
    B. A. Crane, J. A. Githens,Bulk Processing in Distributed Logic Memory, IEEE Trans. on Electronic Computers, Vol. EC-14, No. 2, April 1965, pp. 186–196.Google Scholar
  7. 7.
    R. C. Minnick,A Survey of Microcellular Research, J. ACM., Vol. 14, No. 2, April 1967, pp. 203–241.Google Scholar
  8. 8.
    J. E. Robertson,Two's Complement Multiplication in Binary Parallel Digital Computers, IRE Trans. on Electronic Computers, Sept. 1955, Vol. EC-2, pp. 118–119.Google Scholar
  9. 9.
    S. F. Anderson et al.,The IBM System/360 Model 91: Floating point execution unit, IBM Journal of Research and Development, Vol. 11, No. 1, Jan. 1967, pp. 34–53.Google Scholar
  10. 10.
    B. Elspas, J. Goldberg, R. A. Short and H. S. Stone,Investigation of Propagationlimited Computer networks, Stanford Research Institute, Menlo Park, Calif., Final rept., phase II, Contract AF 19(628)-2902, SRI rept. 4523, prepared for: Electronic Systems Lab., AF Cambridge Research Labs., Office of Aerospace Research, Bedford, Mass., USAF, AFCRL 64-376(II), July 1965, Section IIIA: J. Goldberg,Approaches to the organization of propagation-limited computer systems, pp. 103–114.Google Scholar
  11. 11.
    D. E. Muller,Asynchronous logics and applications to information processing, in: Switching Theory in Space Technology, Stanford, Calif., Stanford Univ. Press, 1963, pp. 289–297.Google Scholar
  12. 12.
    R. McNaughton,Badly timed elements and well timed nets, Report No. 65-02 from: Moore School of Electrical Engineering, Univ. of Penn., June 1964.Google Scholar
  13. 13.
    J. Goldberg, R. A. Short,Antiparallel Control Logic, IEEE Trans. on Electronic Computers, Vol. EC-14, No. 3, June 1965, pp. 383–393.Google Scholar
  14. 14.
    H. H. Loomis, M. R. McCoy,A Theory of High-Speed Clocked Logic, 1965 IEEE Conf. Record: 6th Annual Symp. on Switching Circuit Theory and Logical Design, Oct. 6–8, IEEE Spec.publ. 16 C 13, Oct. 1965, pp. 150–161.Google Scholar
  15. 15.
    R. C. Minnick, R. A. Short,Investigation of Cellular Linear Input Logic, Stanford Research Institute, Menlo Park, Calif., Final rept. Contract AF 19(628)-498, SRI project no. 4122. Prepared for the: Data Sciences Lab., AF Cambridge Research Labs., Bedford, Mass., USAF, AFCRL 64-6, Feb. 1964. Sections IIIA 2 and 4:Autosynchronous logic, Speed Independent implementation, Section IIID:Iterative circuit registers for asynchronous propagation.Google Scholar
  16. 16.
    R. E. Miller,Switching Theory, Vol. II, Chapter 10:Speed independent switching circuit theory, J. Wiley, N.Y., 1965.Google Scholar
  17. 17.
    R. E. Swartwout,One method for designing speed-independent logic for a control, Proc. of the 2nd annual symp. on: Switching Circuit Theory and Logical Design, Detroit 1961, AIEEE Publ. S 134.Google Scholar
  18. 18.
    R. E. Swartwout,New Techniques for designing speed-independent control logic, Proc. of the 5th annual symp. on: Switching Circuit Theory and Logical Design, Princeton, 1964, IEEE Publ. S-164, Oct. 1964, pp. 12–29.Google Scholar
  19. 19.
    R. McNaughton,Finite Automata and Badly Timed Elements, Proc. 4th annual symp. on: Switching Circuit Theory and Logical Design, Oct. 1963, IEEE Publ. Sept. 1963, S-156, pp. 117–130.Google Scholar
  20. 20.
    H. H. Loomis,The Maximum rate Accumulator, IEEE Trans. on Electronic Computers, Vol. EC-15, No. 4, Aug. 1966, pp. 628–639.Google Scholar
  21. 21.
    H. H. Loomis,Delay of synchronous logic nets, 1964 Proc. ACM Nat'l. Conf., pp. A1.2-1 to A1.2-10.Google Scholar
  22. 22.
    D. A. Huffman,The synthesis of Linear Sequential Coding Networks, Proc. of the Third London Symp. on Information Theory, Sept. 1955, Academic Press, N.Y., 1956, pp. 77–95.Google Scholar
  23. 23.
    see [15], page 68, section IIB,Adder arrays.Google Scholar
  24. 24.
    D. N. Senzig and R. V. Smith,Computer Organization for Array Processing, Fall Joint Comp. Conf. 1965, pp. 117–128.Google Scholar
  25. 25.
    J. F. Ruggerio and D. A. Coryell,An Auxiliary Processing System for Array Calculations, IBM Systems Journal, Vol. 8, No. 2, 1969, pp. 118–135.Google Scholar
  26. 26.
    R. Aschenbrenner, M. J. Flynn, G. A. Robinson,Intrinsic Multiprocessing, Spring Joint Comp. Conf., pp. 81–86, 1967.Google Scholar
  27. 27.
    D. N. Senzig,Observations on High-Performance Machines, Spring Joint Comp. Conf., 1967, pp. 791–799.Google Scholar
  28. 28.
    W. H. Kautz,Cellular Logic-in-Memory Arrays, IEEE, Trans. on Computers, Vol. C-18, No. 8, pp. 719–727, 1969.Google Scholar
  29. 29.
    W. H. Kautz,An Augmented Content-Addressable Memory Array for Implementation with Large-Scale Integration, Journal of ACM, (to appear).Google Scholar
  30. 30.
    W. H. Kautz,A Cellular Threshold Array, IEEE, Trans. on Computers, No. 5, pp. 680–682, 1967.Google Scholar
  31. 31.
    A. J. Atrubin,A One-Dimensional Real-Time Iterative MultiOlier, IEEE Trans. on Electronic Computers, Vol. EC-14, No. 3, pp. 394–399, June 1965.Google Scholar
  32. 32.
    Chin Tung,Digital Computer Arithmetic, to appear in: “A Survey of Computer Science” edited by Cardenas, Marin & Presser, John Wiley.Google Scholar

Copyright information

© BIT Foundations 1970

Authors and Affiliations

  • Dines Bjørner
    • 1
  1. 1.Laboratory for Pulse and Digital TechniquesThe Technical University of DenmarkLyngbyDenmark

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