# A flow-mode, self-steering, cellular multiplier-summation processor

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## Abstract

Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2*N* bit for addition and subtraction operands, and*N* bit for multiplication operands. Results are 2*N* bit. The network can simultaneously operate on 4*N*+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.

## Keywords

Cellular Logic Iterative Array Vector Processing Flow Mode Self-Steering Asynchronous Control Arithmetic## CR categories

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