BIT Numerical Mathematics

, Volume 10, Issue 2, pp 125–144 | Cite as

A flow-mode, self-steering, cellular multiplier-summation processor

  • Dines Bjørner


Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.


Cellular Logic Iterative Array Vector Processing Flow Mode Self-Steering Asynchronous Control Arithmetic 

CR categories

6.1 6.32 6.33 


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Copyright information

© BIT Foundations 1970

Authors and Affiliations

  • Dines Bjørner
    • 1
  1. 1.Laboratory for Pulse and Digital TechniquesThe Technical University of DenmarkLyngbyDenmark

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