Competitive snoopy caching Article Received: 28 October 1986 Revised: 30 May 1987 DOI:
Cite this article as: Karlin, A.R., Manasse, M.S., Rudolph, L. et al. Algorithmica (1988) 3: 79. doi:10.1007/BF01762111 Abstract
In a snoopy cache multiprocessor system, each processor has a cache in which it stores blocks of data. Each cache is connected to a bus used to communicate with the other caches and with main memory. Each cache monitors the activity on the bus and in its own processor and decides which blocks of data to keep and which to discard. For several of the proposed architectures for snoopy caching systems, we present new on-line algorithms to be used by the caches to decide which blocks to retain and which to drop in order to minimize communication over the bus. We prove that, for any sequence of operations, our algorithms' communication costs are within a constant factor of the minimum required for that sequence; for some of our algorithms we prove that no on-line algorithm has this property with a smaller constant.
Key words Shared-bus multiprocessors Amortized analysis Potential functions Page replacement Shared memory Cache coherence
A preliminary and condensed version of this paper appeared in the
Proceedings of the 27th Annual Symposium on the Foundations of Computer Science, IEEE, 1986.
This author received support from an IBM doctoral fellowship, and did part of this work while a research student associate at IBM Almaden Research Center.
Communicated by Jeffrey Scott Vitter.
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© Springer-Verlag New York Inc. 1988