Advertisement

Springer Nature is making Coronavirus research free. View research | View latest news | Sign up for updates

Partitioning circuits for improved testability

  • 64 Accesses

  • 19 Citations

Abstract

Exhaustive self-testing of combinational circuitry within the framework of the level-sensitive scan design (LSSD) discipline requires that every output node depend on a small number of input nodes. We present here efficient algorithms that take an arbitrary block of combinational logic and add to it the smallest number of bits of new LSSD registers necessary to: (1) partition the logic so that no output depends on more thank inputs, and (2) maintain timing within the block (so that all input-to-output paths encounter the same number of bits of register). Our partitioning algorithms conform to two different design constraints. We also show that the unconstrained partitioning problem is NP-complete.

This is a preview of subscription content, log in to check access.

References

  1. [1]

    Z. Barzilai, J. L. Carter, A. K. Chandra, and B. K. Rosen, Diagnosis Based on Signature Testing, IBM Report RC-9682 (1983).

  2. [2]

    Z. Barzilai, D. Coppersmith, and A. L. Rosenberg, Exhaustive bit-pattern generation, with applications to VLSI self-testing,IEEE Trans. Comput. 32 (1983), 190–194.

  3. [3]

    J. L. Carter, The theory of signature testing for VLSIProc. 14th ACM Symp. on Theory of Computing, 1982, pp. 66–76.

  4. [4]

    R. David, Testing by feedback shift register,IEEE Trans. Comput.,29 (1980), 668–673.

  5. [5]

    J. Doenhardt, Partitioning circuits for improved testability—a comparison of various methods, Typescript, 1986.

  6. [6]

    E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability,J. Design Automation and Fault-tolerant Comput.,21 (1978), 165–178.

  7. [7]

    M. R. Garey and D. S. Johnson.Computers and Intractability: A Guide to the Theory of NP-Completeness, Freeman, San Francisco, 1979.

  8. [8]

    B. Konemann, J. Mucha, and G. Zwiehoff. Built-in test for complex digital integrated circuits,IEEE J. Solid-State and Circuits,15 (1980).

  9. [9]

    C. E. Leiserson, F. Rose, and J. B. Saxe, Optimizing synchronous circuitry by retiming,Proc. 3rd CalTech Conf. on VLSI, 1983, pp. 87–116.

  10. [10]

    C. E. Leiserson and J. B. Saxe, Optimizing synchronous systems,J. VLSI Comput. Systems,1 (1984), 41–67.

  11. [11]

    E. J. McCluskey and S. Bozorgui-Nesbat, Design for autonomous test,IEEE Trans. Comput.,30 (1981), 866–874.

  12. [12]

    W. W. Peterson,Error Correcting Codes, MIT Press, Cambridge, MA, 1961.

  13. [13]

    D. T. Tang and C. L. Chen, Efficient Exhaustive Pattern Generation for Logic Testing, IBM Report RC-10064 (1983).

  14. [14]

    D. T. Tang and L. S. Woo, Exhaustive test pattern generation with constant weight vectors,IEEE Trans. Comput.,32 (1983), 1145–1150.

Download references

Author information

Additional information

A portion of the research of the first and third authors was done while visiting Bell Communications Research. Sandeep Bhatt was also supported in part by NSF Grant DCR 84-05478 and ONR Grant N00014-82-K-0184, and Arnold Rosenberg by NSF Grants MCS-81-01213 and DMC-85-04308. A preliminary version of this paper was presented at the Fourth MIT VLSI Conference on Advanced Research in VLSI.

Communicated by A. S. LaPaugh.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Bhatt, S.N., Chung, F.R.K. & Rosenberg, A.L. Partitioning circuits for improved testability. Algorithmica 6, 37–48 (1991). https://doi.org/10.1007/BF01759033

Download citation

Key words

  • Circuit testing
  • LSSD
  • Partitioning
  • Dynamic programming
  • NP-completeness