## Abstract

This paper describes a circuit transformation called*retiming* in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set*V* is a collection of combinational logic elements and the edge set*E* is the set of interconnections, each of which may pass through zero or more registers. We give an*O*(¦*V*∥*E*¦lg¦*V*¦) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a chacterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.

## Key words

Digital circuitry Graph theory Linear programming Network flow Optimization Pipelining Propagation delay Retiming Synchronous circuitry Systolic circuits Timing analysis## Preview

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