Formal Methods in System Design

, Volume 6, Issue 2, pp 217–232 | Cite as

Verification of the Futurebus+ cache coherence protocol

  • Edmund M. Clarke
  • Orna Grumberg
  • Hiromi Hiraishi
  • Somesh Jha
  • David E. Long
  • Kenneth L. McMillan
  • Linda A. Ness
Article

Abstract

We used a hardware description language to construct a formal model of the cache coherence protocol described in the IEEE Futurebus+standard. By applying temporal logic model checking techniques, we found errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+boards.

Keywords

The computer industry, standards, Futurebus+ multiple data stream architectures, interconnection architectures network protocols, protocol verification 

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Copyright information

© Kluwer Academic Publishers 1995

Authors and Affiliations

  • Edmund M. Clarke
    • 1
  • Orna Grumberg
    • 2
  • Hiromi Hiraishi
    • 3
  • Somesh Jha
    • 4
  • David E. Long
    • 4
  • Kenneth L. McMillan
    • 4
  • Linda A. Ness
    • 5
  1. 1.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  2. 2.Computer Science DepartmentThe TechnionHaifaIsrael
  3. 3.Department of Information and Communication SciencesKyoto Sangyo UniversityKyotoJapan
  4. 4.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  5. 5.MorristownUSA

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