Low-power architectural synthesis and the impact of exploiting locality

  • Renu Mehra
  • Lisa M. Guerra
  • Jan M. Rabaey


Recently there has been increased interest in the development of high-level architectural synthesis tools targeting power optimization. In this paper, we first present an overview of the various architecture synthesis tasks and analyze their influence on power consumption. A survey of previously proposed techniques is given, and areas of opportunity are identified. We next propose a new architecture synthesis technique for low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. Preserving locality results in more compact layouts, reduced usage of long high-capacitance buses, and reduced power consumption in multiplexors and buffers. Experimental results show reductions in bus and multiplexor power of up to 80% and 60%, respectively, resulting in 10–25% reduction in total power.


Functional Unit Register File Local Assignment Hardware Unit Area Penalty 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Renu Mehra
    • 1
  • Lisa M. Guerra
    • 1
  • Jan M. Rabaey
    • 1
  1. 1.Department of EECSUniversity of California at BerkeleyBerkeleyUSA

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