Reconfiguration algorithms are proposed for VLSI systolic arrays constructed from identical self-testing processors. The properties of fault-tolerant arrays with fixed size and structure degradation are considered.
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Translated from Kibernetika i Sistemnyi Analiz, No. 4, pp. 153–162, July–August, 1992.
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Kharchenko, V.S., Litvinenko, V.G. & Krasnobaev, V.A. Reconfigurable systolic arrays with fixed size and structure degradation. Cybern Syst Anal 28, 623–631 (1992). https://doi.org/10.1007/BF01124999
- Operating System
- Artificial Intelligence
- System Theory
- Fixed Size
- Systolic Array