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Reconfigurable systolic arrays with fixed size and structure degradation

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Abstract

Reconfiguration algorithms are proposed for VLSI systolic arrays constructed from identical self-testing processors. The properties of fault-tolerant arrays with fixed size and structure degradation are considered.

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References

  1. 1.

    H. T. Kung et al., "Systolic arrays for VLSI," Sparse Matrix Proceedings 1978, SIAM (1979), pp. 256–282.

  2. 2.

    W. R. Moore, "A survey of fault-tolerance methods increasing the yield of good integrated circuits," Proc. IEEE,74, No. 5 (1986).

  3. 3.

    M. Sami and R. Stefanelli, "Reconfigurable architectures for VLSI processing arrays," Proc. IEEE,74, No. 5, 712–722 (1986).

  4. 4.

    R. Negrini, M. G. Sami, and R. Stefanelli, "Fault-tolerance approaches for VLSI/WSI arrays," IEEE Conf. on Computers and Communications, Phoenix, AZ (1985).

  5. 5.

    S. A. Dolgushev, V. N. Doniants, and R. Stefanelli, "Algorithmic fault-tolerance methods for homogeneous VLSI processing arrays," in: Control in Distributed Information Systems [in Russian], Nauka, Moscow (1989), pp. 61–74.

  6. 6.

    S. A. Dolgushev and V. N. Doniants, "Choosing the reconfiguration direction in homogeneous VLSI processing arrays," in: Control in Distributed Information Systems [in Russian], Nauka, Moscow (1989), pp. 84–93.

  7. 7.

    A. I. Galushkin, L. V. Grachev, M. M. Tolstykh, and V. A. Tochenov, "Assessment of reconfiguration algorithms for MIMD architectures," Kibernetika, No. 2, 35–41 (1990).

  8. 8.

    D. S. Perloff et al., "Microelectronic test chips in integrated circuits manufacturing," Solid State Techn., 75–80 (Sept. 1981).

  9. 9.

    T. Motooka, H. Horikosi, M. Sakauti, et al., VLSI Computers [Russian translation], Mir, Moscow (1988).

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Additional information

Translated from Kibernetika i Sistemnyi Analiz, No. 4, pp. 153–162, July–August, 1992.

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Kharchenko, V.S., Litvinenko, V.G. & Krasnobaev, V.A. Reconfigurable systolic arrays with fixed size and structure degradation. Cybern Syst Anal 28, 623–631 (1992). https://doi.org/10.1007/BF01124999

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Keywords

  • Operating System
  • Artificial Intelligence
  • System Theory
  • Fixed Size
  • Systolic Array