Journal of Electronic Testing

, Volume 5, Issue 1, pp 43–55

Incorporating testability considerations in high-level synthesis

  • Ashutosh Mujumdar
  • Rajiv Jain
  • Kewal Saluja
Design and Synthesis for Testability


In this article we propose two novel methods to improve the testability of the designs produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies self-loops in a design generated by a high-level synthesis system and eliminates as many of these loops as possible by altering the register and module bindings. The second method, BINET with test cost, is a binding algorithm that takes the cost of testing into account during the binding phase of the high-level synthesis. The test cost considered in this article is a function of the number of self-loops in the synthesized design. Thus it generates only those solutions that have fewer if any self-loops. Finally we put the two methods together in which we first use BINET with test cost to produce nearly self-loop free designs and we further improve their testability by using the loop-breaking algorithm. We applied these methods to synthesis benchmark circuits and the results of our study, given in this article, show that the designs produced by our method have indeed reduced testability overhead and improved testability.


Automatic synthesis of testable designs binding high-level synthesis loop breaking synthesis for testability 


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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • Ashutosh Mujumdar
    • 1
  • Rajiv Jain
    • 1
  • Kewal Saluja
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of WisconsinMadison

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