Journal of Electronic Testing

, Volume 4, Issue 2, pp 137–150 | Cite as

An architectural level test generator based on nonlinear equation solving

  • Jaushin Lee
  • Janak H. Patel


It has been shown that the hierarchy of large VLSI circuits can be exploited to speed up the test generation process. However, severe problems remain in most of the published literature which were based on a high level branch-and-bound approach. When the circuit module diagram is complex, it is very difficult to formalize the high level knowledge derived from the circuit hierarchy to make successful decisions in searching. Whenever a global path conflict or value conflict happens, it is unlikely that the backtracking scheme is able to solve this conflict through high level knowledge manipulation. In this article, a new architectural level test generation algorithm based on a nonlinear equation-solving methodology is proposed to solve conflicts and avoid making high level decisions when the tests are computed. For each pattern to be justified at a high level, an instruction sequence and the under-determined system of nonlinear equations are derived based on preprocessing information. The solution of the system of equations are calculated by a signal-driven discrete relaxation algorithm without making any high level decision. The test generation is performed by recursively assembling the instruction sequence and solving the system of equations. This new test generation approach has been implemented, and the tests of several microprocessors have been generated successfully. The results show that this approach is effective and promising.


Hierarchical test generation module diagram nonlinear module equation relaxation technique symbolic simulation 


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Copyright information

© Kluwer Academic Publishers 1993

Authors and Affiliations

  • Jaushin Lee
    • 1
  • Janak H. Patel
    • 1
  1. 1.Center for Reliable and High-Performance Computing, Coordinated Science LaboratoryUniversity of Illinois at Urbana-ChampaignUrbana

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