Gate array implementation of on-line algorithms for floating-point operations
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We present gate array designs of on-line arithmetic units for radix-2 floating-point addition, multiplication and division operations. Performance and complexity characteristics of the implementations of on-line arithmetic units are discussed and compared with those of the compatible conventional floating-point algorithms implemented in the same technology.
KeywordsGate Count Quotient Digit Digit Selection Result Digit Digit Multiplier
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