Gate array implementation of on-line algorithms for floating-point operations

  • Paul K. -G. Tu
  • Miloŝ D. Ercegovac


We present gate array designs of on-line arithmetic units for radix-2 floating-point addition, multiplication and division operations. Performance and complexity characteristics of the implementations of on-line arithmetic units are discussed and compared with those of the compatible conventional floating-point algorithms implemented in the same technology.


Gate Count Quotient Digit Digit Selection Result Digit Digit Multiplier 
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Copyright information

© Kluwer Academic Publishers 1991

Authors and Affiliations

  • Paul K. -G. Tu
    • 1
  • Miloŝ D. Ercegovac
    • 2
  1. 1.Advanced Workstation DivisionIBM CorporationAustin
  2. 2.Computer Science DepartmentUniversity of CaliforniaLos Angeles

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