Cost-efficient high-radix division
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Digital signal processing implementations require fast and efficient arithmetic units. This paper proposes a fast, cost-efficient enhancement to high-radix, recursive dividers. Recursive dividers are commonly implemented using a subtractor and/or a multiplier, and hardware to determine an estimate of the quotient. Traditionally, these dividers have required an off-chip ROM or a large programmable logic array (PLA) to store a truncated quotient estimate. An interesting alternative is to simplify the hardware realization with a less accurate estimate of the quotient. This paper introduces an algorithm of this type called the expanded redundancy method which is based on Renato Stefanelli's algorithm and a further enhancement by David Mandelbaum.
This study compares implementations of byte-quotient estimators (radix-256) using a ROM look-up table, a direct combinational switching network, and the proposed expanded redundancy method. The estimators will be compared by area (in terms of gate count), by gate levels of delay, and by accuracy (in terms of number of iterations to converge). Three recursive algorithms are used for this comparison: 1) nonrestoring method, 2) constant convergence method, and 3) quadratic convergence method. This study will show that the proposed implementation of a byte-quotient estimator is comparable in gate delay and accuracy and can easily be integrated on-chip with other division hardware.
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