Cost-efficient high-radix division

  • Eric M. Schwarz
  • Michael J. Flynn
Article

Abstract

Digital signal processing implementations require fast and efficient arithmetic units. This paper proposes a fast, cost-efficient enhancement to high-radix, recursive dividers. Recursive dividers are commonly implemented using a subtractor and/or a multiplier, and hardware to determine an estimate of the quotient. Traditionally, these dividers have required an off-chip ROM or a large programmable logic array (PLA) to store a truncated quotient estimate. An interesting alternative is to simplify the hardware realization with a less accurate estimate of the quotient. This paper introduces an algorithm of this type called the expanded redundancy method which is based on Renato Stefanelli's algorithm and a further enhancement by David Mandelbaum.

This study compares implementations of byte-quotient estimators (radix-256) using a ROM look-up table, a direct combinational switching network, and the proposed expanded redundancy method. The estimators will be compared by area (in terms of gate count), by gate levels of delay, and by accuracy (in terms of number of iterations to converge). Three recursive algorithms are used for this comparison: 1) nonrestoring method, 2) constant convergence method, and 3) quadratic convergence method. This study will show that the proposed implementation of a byte-quotient estimator is comparable in gate delay and accuracy and can easily be integrated on-chip with other division hardware.

References

  1. 1.
    P. Markenstein, “Computation of elementary functions on the IBM RISC system/6000 processor,”IBM Journal of Research and Development, vol. 34, 1990, pp 111–129.CrossRefGoogle Scholar
  2. 2.
    D.A. Patterson and J.L. Hennessy,Computer Architecture: A Quantitative Approach, San Mateo, CA: Morgan Kaufman, 1990.Google Scholar
  3. 3.
    S. Waser and M.J. Flynn,Introduction to Arithmetic for Digital Systems Designers New York: CBS College Publishing, Ch. 5, 1982.Google Scholar
  4. 4.
    D.E. Atkins, “A study of methods for selection of quotient digits during digital division,”Ph.D. Dissertation, Report 397, Dept. of Computer Science, Univ. of Illinois, Urbana, June 1965.Google Scholar
  5. 5.
    R. Stefanelli, “A suggestion for a high-speed parallel binary divider,”IEEE Trans. Comput., vol. C-21, 1972, pp. 42–55.CrossRefMATHGoogle Scholar
  6. 6.
    D.M. Mandelbaum, “A systematic method for division with high average bit skipping,”IEEE Trans. Comput., vol. 39, 1990, pp. 127–130.CrossRefGoogle Scholar
  7. 7.
    D.M. Mandelbaum, “Some results on a SRT type division scheme”, private written communication, Nov. 8, 1990.Google Scholar
  8. 8.
    L. Dadda, “Some schemes for parallel multipliers,”Alta Frequenza, vol. 34, 1965, pp. 349–356.Google Scholar
  9. 9.
    S.D. Pezaris, “A 40-ns 17-bit by 17-bit array multiplier,”IEEE Trans. Comput., vol. C-20, 1971, pp. 442–447.CrossRefGoogle Scholar
  10. 10.
    T.M. Carter and J.E. Robertson, “Radix-16 signed-digit division,”IEEE Trans. Comput., vol. 39, 1990, pp. 1424–1433.CrossRefGoogle Scholar
  11. 11.
    C.S. Wallace, “A suggestion for a fast multiplier,”IEEE Trans Comput., vol. EC-13, 1964, pp. 14–17.CrossRefMATHGoogle Scholar
  12. 12.
    S. Vassiliadis, E.M. Schwarz, and B.M. Sung, “Hard-wired multipliers with encoded partial products,”IEEE Trans. Comput., 1991.Google Scholar
  13. 13.
    N. Takagi, et al., “High-speed VLSI multiplication algorithm with a redundant binary addition tree,”IEEE Trans. Comput., vol. C-34, 1985, pp. 789–796.CrossRefMATHGoogle Scholar
  14. 14.
    D. Wong and M.J. Flynn, “Fast division using accurate quotient approximations to reduce the number of iterations,”IEEE 10th Symp. on Comput. Arith., 1991, pp. 191–201.Google Scholar
  15. 15.
    K. Hwang,Computer Arithmetic: Principles Architecture, and Design, New York: Wiley, Ch. 7, 8, and 11, 1979.Google Scholar
  16. 16.
    M.J. Flynn, “On division by functional iteration,”IEEE Trans. Comput. vol. C-19, 1970, pp. 702–706.CrossRefMATHGoogle Scholar
  17. 17.
    R.E. Goldschmidt, “Applicaitons of division by convergence”, Master's Thesis, M.I.T., June 1964.Google Scholar
  18. 18.
    S.F. Anderson, et al., “The IBM system/360 model 91: floatingpoint execution unit”,IBM Journal of Research and Development, 1967, pp. 34–53.Google Scholar

Copyright information

© Kluwer Academic Publishers 1991

Authors and Affiliations

  • Eric M. Schwarz
    • 1
  • Michael J. Flynn
    • 1
  1. 1.Computer Systems LaboratoryStanford UniversityStanford

Personalised recommendations