High-performance VLSI multiplier with a new redundant binary coding

  • Xiaoping Huang
  • Belle W. Y. Wei
  • Honglu Chen
  • Yuhai H. Mao
Article

Abstract

This paper describes the design of a 16×16 redundant binary multiplier for signed 2's complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.

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Copyright information

© Kluwer Academic Publishers 1991

Authors and Affiliations

  • Xiaoping Huang
    • 1
  • Belle W. Y. Wei
    • 1
  • Honglu Chen
    • 2
  • Yuhai H. Mao
    • 2
  1. 1.Department of Electrical EngineeringSan Jose State UniversitySan Jose
  2. 2.Department of RadioelectronicsTsinghua UniversityBeijingPeople's Republic of China

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