High-performance VLSI multiplier with a new redundant binary coding
- 58 Downloads
This paper describes the design of a 16×16 redundant binary multiplier for signed 2's complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.
Unable to display preview. Download preview PDF.
- 2.K.F. Pang, et al. “Generation of High Speed CMOS Multiplier-Accumulator,”IEEE International conference on Computer Design (ICCD 88),Google Scholar
- 3.M. Birman, et al. “Desig of a High-Speed Arithmetic Datapath,”IEEE International Conference on Computer Design (ICCD 88), pp. 214–216.Google Scholar
- 5.S. Waser and M.J. Flynn,Introduction to Arithmetic for Digial Systems Designers, New York: Holt, Rinehart, and Winston, 1982.Google Scholar
- 6.Naofumi Takagi, Hiroto Yasuura, and Shuzo Yajima, “High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,”IEEE Trans. on Computers, vol. C-34, 1985.Google Scholar
- 7.Shigeo Kuniobu, et al., “Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation,”8th Symposium on Computer Arithmetic, 1987, pp. 80–86.Google Scholar
- 8.Hisakazu Edamatsu, et al., “A 33 MFLOPS Floating Point Processor using Redundant Binary Representation,”1988 ISSCC Digest of Technical Papers, 1988, pp. 152–153.Google Scholar
- 10.Catherine Chow and James Robertson, “Logical Design of a Redundant Binary Adder,”4th Symposium on Computer Arithmetic, 1978, pp. 109–115.Google Scholar
- 11.N. Weste and K. Eshraghian,Principles of CMOS VLSI Design: A System Perspective, Reading, MA: Addison-Wesley, 1985.Google Scholar