CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench
Application of the Object-Oriented Design of Reliable/Reconfigurable Architectures (OODRA) workbench to the performance simulation of a reconfigurable adaptive digital beamforming architecture is described in this paper. The performance effects due to chip/wafer partitioning and reconfiguration for fault tolerance and yield enhancement are presented. The experiments described illustrate use of the OODRA workbench in architectural-level performance evaluation of algorithm-specific reconfigurable architectures, particularly for signal processing applications.
Key wordsapplication-specific architecture simulation object-oriented design reconfiguration evaluation
Unable to display preview. Download preview PDF.
- 1.W.K. Fuchs et al., “The Impact of Parallel Architecture Granularity on Yield”, in Moore, Maly and Strojwas, eds.Yield Modeling and Defect Tolerance in VLSI, London: Adam Hilger, pp. 163–174, 1988.Google Scholar
- 2.S.Y. Kuo and W.K. Fuchs, “Spare Allocation and Reconfiguration in Large Area VLSI”,Proc. ACM/IEEE Design Automation Conference, pp. 609–612, 1988.Google Scholar
- 3.D.K. Hwang and W.K. Fuchs, “CSP-Based Object-Oriented Description of Paralel Reconfigurable Architectures”,Proc. IEEE Int. Conf. on Wafer Scale Integration, pp. 111–120, 1989.Google Scholar
- 6.G. Frank, D. Franke, and W. Ingogly, “An Architecture Design and Assessment System,”VLSI Design, pp. 30–50, Aug. 1985.Google Scholar
- 7.F. Distante and V. Piuri, “APES: An Integrated System for Behavioral Design, Simulation and Evaluation of Array Processors,”Proc. IEEE Int. Conf. on Computer Design, pp. 568–572, 1988.Google Scholar
- 8.A. Krishnakumar, “ART-DACO: Architectural Research Tool Using Data Abstraction and Concurrency,”Proc. IEEE Int. Conf. on Computer Design, pp. 18–21, 1987.Google Scholar
- 10.J.V. McCanny and J.G. McWhirter, “Some Systolic Array Developments in the United Kingdom,”Computer, pp. 51–63, July 1987.Google Scholar
- 12.M. Linton and P. Calder, “The Design and Implementation of InterViews,” inUSENIX C++ Conference, pp. 256–267, 1987.Google Scholar
- 15.M. McFarLand, A. Parker, and R. Camposano, “Tutorial on High-Level Synthesis,”Proc. ACM/IEEE Design Automation Conference, (Anaheim), pp. 330–336, 1988.Google Scholar
- 16.D.E. Thomas et al., “The System Architect's Workbench,”Proc. ACM/IEEE Design Automation Conference, pp. 337–343, 1988.Google Scholar
- 18.D.S. Broomhead et al., “A Practical Comparison of the Systolic and Wavefront Array Processing Architectures,”IEEE Workshop on VLSI Signal Processing, (Los Angeles), pp. 375–386, 1984.Google Scholar
- 19.B. Krishnamurthy and P. Mellema, “On the Evaluation of Min-Cut Partitioning Algorithms for VLSI Networks,”International Symp. on Circuits and Systems, pp. 12–15, 1983.Google Scholar