Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

A low-overhead scheme for testing a bit-level finite ring systolic array

  • 25 Accesses

  • 9 Citations

Abstract

Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to generate using automated tools for testing. In this paper, we have investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions. The cell has been shown to allow encoding, decoding and general inner product type computations for residue number system applications, with considerable advantages over equivalent binary implementation. As a further feature, we show, in this paper, that an array of such cells is remarkably easy to test for stuck-at faults. Generating test vectors for these arrays is also straightforward.

This is a preview of subscription content, log in to check access.

References

  1. 1.

    H.T. Kung, “Why Systolic Architectures?,”IEEE Computer Magazine, vol. 15, Jan. 1982, pp. 37–46.

  2. 2.

    M. Taheri, G.A. Jullien, and W.C. Miller, “High-Speed Signal Processing Using Systolic Arrays Over Finite Rings,”IEEE Journal of Selected Areas in Communications, April, 1988.

  3. 3.

    W. Moore, A. McCabe and R. Urquhart, eds.Systolic Arrays. Adam Hilger, Bristol, 1986.

  4. 4.

    J.V. McCanny, R.A. Evans, and J.G. McWhirter, “Use of Unidirectional Data Flow in Bit Level Systolic Array Chips,”Electronics Letters, vol. 22, 1986, pp. 540–541.

  5. 5.

    M.A. Soderstrand, W.K. Jenkins, G.A. Jullien, F.J. Taylor,Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, New York: IEEE Press, 1986.

  6. 6.

    G.A. Jullien, P.D. Bird, J.T. Carr, M. Taheri, W.C. Miller, “An Efficient Bit-Level Systolic Cell Design for Finite Ring Digital Signal Processing Applications,”Journal of VLSI Signal Processing, vol. 1, 1989, pp. 189–207.

  7. 7.

    M. Taheri, “VLSI Fault-Tolerant Systolic Architectures,” Ph.D thesis, Electrical Engineering, University of Windsor, 1988.

  8. 8.

    A.D. Friedman and P.R. Menon,Fault Detection in Digital Circuits, Englewood Cliffs: Prentice Hall, 1971.

  9. 9.

    T.W. Williams, “VLSI Testing,”IEEE Computer Magazine, vol. 17, Oct. 1984, pp. 126–136.

  10. 10.

    J.A. Abraham and W.K. Fuchs, “Fault and Error Models for VLSI,”Proc IEEE, vol. 74, 1986, pp. 639–654.

  11. 11.

    W.T. Chung and J.H. Patel, “A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders,”IEEE Trans. Computers, vol. C-36, 1987, pp. 891–895.

  12. 12.

    R. Parthasarathi and S.M. Reddy, “A Testable Desgn of Iterative Logic Array,”IEEE Trans. Computers, vol. C-30, 1981, pp. 833–841.

  13. 13.

    J.P. Shan and F.J. Ferguson, “The Design of Easily Testable VLSI Array Multipliers,”IEEE Trans. Computers, vol. C-33, 1984, pp. 554–560.

  14. 14.

    E.M. Aboulhamid and E. Cerny, “Built-in Testing of One-Dimensional Unilateral Iterative Arrays,”IEEE Trans. Computers, vol. C-33, 1984, pp. 560–564.

  15. 15.

    J. Savir, “Syndrome Testable Design of Combinational Circuits,”IEEE Trans. Computers, vol. C-29, 1980, pp. 442–451.

  16. 16.

    K.K. Saluja, K. Kinoshita and H. Fujiwara, “An Easily Testable Design of Programmable Logic Arrays for Multiple Faults,”IEEE Trans. Computers, vol. C-32, 1983, pp. 1038–1046.

  17. 17.

    W.P. Marmane and W.R. Moore, “A computational Approach to Testing Regular Arrays,” inSystolic Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1989, pp. 577–586.

  18. 18.

    K. Hwang and F.A. Briggs,Computer Architecture and Parallel Processing, New York: McGraw Hill, 1984.

  19. 19.

    D.I. Moldovan, “On the Design of Algorithms for VLSI Systolic Arrays,”Proc. IEEE, vol. 71, 1983, pp. 113–120.

  20. 20.

    M.J.Y. Williams and J.B. Angell, “Enhancing Testability of Large Scale Integrated Circuits via Testpoint and Additional Logic,”IEEE Trans. Computers, vol. C-22, 1973, pp. 46–60.

  21. 21.

    E.J. McCluskey,Logic Design Principles: with Emphasis on Semicustom Circuits, Englewood Cliffs, N.J.: Prentice Hall, 1986.

  22. 22.

    A. Friedman, “Easily Testable Iterative Systems,”IEEE Trans. Computers, vol. C-22, 1973, pp. 1061–1064.

Download references

Author information

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Jullien, G.A., Bandyopadhyay, S., Miller, W.C. et al. A low-overhead scheme for testing a bit-level finite ring systolic array. J VLSI Sign Process Syst Sign Image Video Technol 2, 131–137 (1990). https://doi.org/10.1007/BF00935210

Download citation

Keywords

  • Digital Signal Processing
  • Data Path
  • Test Vector
  • Systolic Array
  • Residue Number System