An efficient tree architecture for modulo 2 n +1 multiplication

  • Zhongde Wang
  • G. A. Jullien
  • W. C. Miller
Article
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Abstract

Modulo 2 n +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most suitable for representing the elements of the rings. Existing algorithms for modulo (2 n +1) multiplication either use recursive modulo (2 n +1) addition, or a regular binary multiplication integrated with the modulo reduction operation. Although most often adopted for largen, this latter approach requires conversions between the diminished-1 and binary representations. In this paper we propose a parallel fine-grained architecture, based on a Wallace tree, for modulo (2 n +1) multiplication which does not require any conversions; the use of a Wallace tree considerably improves the speed of the multiplier. This new architecture exhibits an extremely modular structure with associated VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a correspondingn×n bit binary multiplier.

Keywords

Partial Product Full Adder Residue Number System Fermat Number Critical Path Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Zhongde Wang
    • 1
  • G. A. Jullien
    • 1
  • W. C. Miller
    • 1
  1. 1.University of WindsorWindsorCanada

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