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A sorter-based architecture for a parallel implementation of communication intensive algorithms

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Abstract

This paper deals with the parallel execution of algorithms with global and/or irregular data dependencies on a regularly and locally connected processor array. The associated communication problems are solved by the use of a two-dimensional sorting algorithm. The proposed architecture, which is based on a two-dimensional sorting network, offers a high degree of flexibility and allows an efficient mapping of many irregularly structured algorithms. In this architecture a one-dimensional processor array performs all required control and arithmetic operations, whereas the sorter solves complex data transfer problems. The storage capability of the sorting network is also used as memory for data elements. The algorithms for sparse matrix computations, fast Fourier transformation and for the convex hull problem, which are mapped onto this architecture, as well as the simulation of a shared-memory computer show that the utilization of the most complex components, the processors, is O(1).

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Krammer, J.G. A sorter-based architecture for a parallel implementation of communication intensive algorithms. J VLSI Sign Process Syst Sign Image Video Technol 3, 93–103 (1991). https://doi.org/10.1007/BF00927837

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Keywords

  • Data Element
  • Local Memory
  • Connected Region
  • Sorting Algorithm
  • Processor Array