WASP: A WSI Associative String Processor
- 32 Downloads
- 16 Citations
Abstract
ASP (Associative String Processor) modules (and support software) comprise highly-versatile and fault-tolerant building-blocks for the simple construction of dynamically-reconfigurable low-MIMD/high-SIMD second-generation Massively Parallel Processor (MPP) systems. Indeed, based on state-of-the-art microelectronics and packaging technologies, ASP modules constitute a family of packaged MPP configurations for the cost-effective implementation of highly-compact application-specific high performance information processing systems.
Based on scalar-vector content-matching rather than location addressing, ASP substrings comprise homogeneous fine-grain SIMD MPP structures, which, in operation, execute a form of set processing (i.e. a sequence of scalar-vector and vector-vector processes) on relevant data. Moreover, application flexibility enables simple tailoring of parallel processing power to match user requirements.
WASP devices are WSI (Wafer Scale Integration) implementations of ASP substrings and, as such, constitute fundamental building blocks for the assembly of ASP modules. Exploiting either monolithic or hybrid 1 μm CMOS WSI technologies, 8,192-processor WASP devices would enable the assembly of 65,536-processor SEM-E compatible ASP modules achieving 10 Tera-OPS/ft3, 1 Giga-OPS/W and 1 Mega-OPS/$ in cost-effectiveness.
The paper discusses second-generation MPP design targets and describes ASP modules for real-time signal and data processing applications. In particular, the paper focuses on the architecture, operation, and implementation of the WASP device and reports on the progress of its development.
Keywords
Global Memory Packaging Technology Data Communication Network Wafer Scale Integration Input Data RatePreview
Unable to display preview. Download preview PDF.
References
- 1.R.M. Lea, “The ASP: A cost-effective parallel microcomputer,”IEEE Micro, 1988, pp. 10–29.Google Scholar
- 2.R.M. Lea, “ASP modules: Cost-effective building blocks for real-time DSP systems,”Journal of VLSI Signal Processing, 1989, vol. 1, pp. 61–76.CrossRefGoogle Scholar
- 3.R.M. Lea, “A WSI image processor,” Wafer Scale Integration (ed. Swartzlander), Boston, Kluwer Academic Publishers, 1988.Google Scholar
- 4.R.M. Lea, “WASP: A wafer-scale massively parallel processor,” Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Brewer and Little),IEEE Computer Society Press, 1990, pp. 36–42.Google Scholar
- 5.R. Morgan and M. Soraya, “Future military avionics applications of wafer-scale technology,” Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer),IEEE Computer Society Press, 1989, pp. 1–12.Google Scholar
- 6.A. Krikelis and R.M. Lea, “Performance of the ASP on the DARPA architecture benchmark”, Proc. Frontiers 88, 2nd. Symp. on the Frontiers of Massively Parallel Computation, Fairfax, VA, October 1988.Google Scholar
- 7.A. Krikelis,, I. Kossioris and R.M. Lea, “Performance of the ASP on the DARPA architecture benchmark II,” Proc. DARPA Image Understanding Benchmark Workshop, Avon, CT, October 1988.Google Scholar
- 8.S. Lone, R.K. Bock, Y. Ermolin, W. Krischer, C. Ljuslin, K. Zografos, “Fine-grain parallel computer architectures in future triggers,” CERN report CERN-LAA RT/89-05, September 1989.Google Scholar
- 9.I.P. Jalowiecki, K.D. Warren and R.M. Lea, “WASP: A WSI Associative String Processor,” Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer),IEEE Computer Society Press, 1989, pp. 83–93.Google Scholar
- 10.I.P. Jalowiecki and S.J. Hedge, “The WASP demonstrator programme: the engineering of a wafer-scale system,” Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Brewer and Little),IEEE Computer Society Press, 1990, pp. 43–49.Google Scholar
- 11.K.D. Warren, J.H. Reche, W.J. Jacobi and R.M. Lea, “A 3D HDI ASP: A cost-effective alternative to WSI signal processors,” Proc. IEEE Int. Conf. on Wafer Scale Integration (eds. Swartzlander and Brewer),IEEE Computer Society Press, 1989, pp. 267–276.Google Scholar