Mod-2-OBDDs—A data structure that generalizes EXOR-sum-of-products and ordered binary decision diagrams
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We present a data structure for Boolean manipulation-the Mod-2-OBDDs-that considerably extends ESOPs (EXOR-sum-of-products) as well as OBDDs (ordered binary decision diagrams). There are Boolean functions of practical interest which have exponential size optimal ESOPs (even multilevel EXOR-expressions) and/or OBDDs that can be represented by (low degree) polynomial size Mod-2-OBDDs.
We show that Boolean manipulation tasks such as apply operation, quantification, composition can be performed with Mod-2-OBDDs at least as efficient as with OBDDs. Indeed, since the size of a minimal Mod-2-OBDD-representation of a Boolean function is, in general, smaller (sometimes even exponentially smaller) than the size of an optimal OBDD-representation, the increase in efficiency is considerable. Moreover, EXOR-operations as well as complementations can be performed in constant timeO (1).
However, the price of constant time EXOR-apply operations is the canonicity of the Mod-2-OBDD-representation. In order to allow in spite of this fact efficient analysis of Mod-2-OBDDs we present a fast probabilistic equivalence test with one-sided error probability for Mod-2-OBDDs (and, hence, for ESOPs) which performs only linear many arithmetic operations.
Keywordsdata structures for Boolean functions BDDs verification EXOR expressions
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- 1.M. Ajtai, L. Babai, P. Hajnal, J. Komlos, P. Pudlak, V. Rödl, E. Szemeredi, and G. Turan, “Two lower bounds for branching programs,”Proc. 18th ACM STOC, 1986, pp. 30–38.Google Scholar
- 2.B. Becker, “Synthesis for testability: Binary decision diagrams,”Proc. of 9th Annual Symposium on Theoretical Aspects of Computer Science, Lecture Notes in Computer Science, February 1992, Vol 577, pp. 501–512.Google Scholar
- 3.B. Becker and R. Drechsler,On the Computational Power of Functional Decision Diagrams, Interner Bericht 5/93, Universität Frankfurt, 1993.Google Scholar
- 5.S.D. Brown, R.J. Francis, J. Rose, and Z.G. Vranesic,Field-Programmable Gate Arrays, Kluwer Academic Publisher, 1992.Google Scholar
- 6.R.E.Bryant, “Graph-based algorithms for boolean function manipulation,”IEEE Trans. Comput. C-35, Vol. 6, pp. 677–691, August 1986.Google Scholar
- 9.J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill, “Sequential circuit verification using symbolic model checking,”Proc. of 27th ACM/IEEE Design Automation Conference, Orlando, June 1990, pp. 46–51.Google Scholar
- 10.O. Coudert, J.-C. Madre, and C. Berthet, “Verifying temporal properties of sequential machines without building their state diagrams”,Proc. of Computer-Aided Verification, Rutgers, N.J., June 1990, pp. 75–84.Google Scholar
- 11.R. Drechsler and B. Becker,Rapid Prototyping of Fully Testable Multi-Level AND/EXOR Networks, Interner Bericht 4/93, Universität Frankfurt, 1993.Google Scholar
- 12.H.Eveking,Verifikation digitaler Systeme, Teubner, Stuttgart, 1991.Google Scholar
- 13.J. Gergov and Ch. Meinel, “Frontiers of feasible and probabilistic feasible boolean manipulation with branching programs,”Proc. of 10th Annual Symposium on Theoretical Aspects of Computer Science, (February), Lecture Notes in Computer Science, Vol. 665, 1993, pp. 576–585.Google Scholar
- 14.J. Gergov and Ch. Meinel, “Efficient analysis and manipulation of OBDDs can be extended to FBDDs”,IEEE Transactions on Computers, Vol. 43, No. 10, 1994.Google Scholar
- 16.U. Kebschull, E. Shubert, and W. Rosenstiel, “Multilevel logic synthesis based on functional decision diagrams”,Proc. EDAC'92, 1992, pp. 43–47.Google Scholar
- 17.R. Lidl and H. Niederreiter,Introduction to Finite Fields and Their Applications, Cambridge University Press, 1986.Google Scholar
- 18.S. Malik, A. Wang, and R.K. Brayton, “A. Sangiovanni-Vincentelli: Logic verification using binary decision diagrams in a logic synthesis environment”,Proc. IEEE International Conference on Computer-Aided Design, Santa Clara, Calif., November 1988, pp. 6–9.Google Scholar
- 19.Ch. Meinel,Modified Branching Programs and Their Computational Power, Springer Verlag, LNCS 370, 1989.Google Scholar
- 20.H. Minato, N. Ishiura, and S. Yajima, “Shared binary decision diagrams with attributed edges for efficient boolean function manipulation”,Proc. 27th ACM/IEEE Design Automation Conference, Orlando, June 1990, pp. 52–57.Google Scholar
- 21.D.E.Muller, “Application of Boolean algebra to switching circuit design and to error correction,”IRE Trans. Electr. Comp., Vol. 3, No. 3, pp. 6–12, September 1954.Google Scholar
- 22.M.A. Perkowski, L. Csansky, A. Sarabi, and I. Schäfer, “Fast minimization of mixed polarity AND/XOR canonical networks”,Proceedings of ICCD'92, 1992, pp. 33–36.Google Scholar
- 23.A.A. Razborov, “A lower bound on the size of bounded depth networks over a complete basis with logical addition”,Mat. Zametki, Vol. 41, No. 4, pp. 598–607, 1987 (in Russian); English translation in:Math. Notes, Vol. 41, No. 4, pp. 333–338, 1987.Google Scholar
- 27.T. Sasao, ”Optimization of multi-valued AND-EXOR expressions using multiple-place decision diagrams”,Proceedings of the 22nd Int. Symp. of Multi-Valued Logic, 1992, pp. 451–458.Google Scholar
- 28.J.M. Saul, “Logic synthesis for arithmetic circuits using Reed-Muller representation”,Proc. EDAC'92, March 1992.Google Scholar