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Amorphous silicon logic integrated circuits

Abstract

Amorphous silicon thin-film integrated circuits, with between 4 and 18 transistor functions per chip, have been fabricated on glass substrates. The amorphous silicon and the dielectric layers are deposited by rf glow discharge. The circuits have been designed to realize basic logic functions such as inverters, NAND and NOR gates, and addressable memory cells. For the first time, an amorphous silicon flip flop requiring a supply voltage of only 4.5 V has been manufactured. The logic voltage levels of the flip flop are compatible with standard bipolar TTL circuits. Measurements on an inverter chain show a typical propagation delay time of 70 μs and a power-delay-time product of 65 pJ. All of the circuits use n-channel enhancement type load transistors instead of integrated ohmic load resistors. The channel length of the driver transistors is 15 μm with a gate source/drain overlap of 7.5 μm. Experimental geometry ratios range from β=2.25 to β=21. Generally, the driver transistors exhibit on/off ratios greater than 106 for supply voltages smaller than 5 V. At these voltages the measured on-currents per unit channel width are in the order of 5...10nA/μm.

The influence of the geometry ratio on static inverter characteristic and switching speed is discussed by means of a simple model. Two different manufacturing schemes for the fabrication of the integrated circuits are outlined. Mask layouts and experimental transfer characteristics of several integrated circuits are presented.

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Böhm, M., Salamon, S. & Kiss, Z. Amorphous silicon logic integrated circuits. Appl. Phys. A 45, 53–61 (1988). https://doi.org/10.1007/BF00618763

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PACS

  • 61.40
  • 85.30
  • 85.60