Journal of Electronic Testing

, Volume 8, Issue 1, pp 71–86 | Cite as

Balance testing and balance-testable design of logic circuits

  • Krishnendu Chakrabarty
  • John P. Hayes
Design for Testability


We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.


built-in self testing design for testability fault coverage fault detection testing methods 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.Google Scholar
  2. 2.
    J.P. Hayes, “Check Sum Methods for Test Data Compression,” Journal of Design Automation and Fault-Tolerant Computing, vol. 1, pp. 3–7, January 1976.Google Scholar
  3. 3.
    A. Tzidon, I. Berger, and M. Yoeli, “A Practical Approach to Fault Detection in Combinational Circuits,” IEEE Transactions on Computers, vol. C-27, pp. 968–971, October 1978.Google Scholar
  4. 4.
    J. Savir, “Syndrome-Testable Design of Combinational Circuits,” IEEE Transactions on Computers, vol. C-29, pp. 442–451, June 1980.Google Scholar
  5. 5.
    R.A. Frohwerk, “Signature Analysis: A New Digital Field Service Method,” Hewlett-Packard Journal, vol. 28, pp. 2–8, September 1977.Google Scholar
  6. 6.
    K. Chakrabarty, Balanced Boolean Functions, M.S. thesis, Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, September 1992; also published as Technical Report CSE-TR-140–92.Google Scholar
  7. 7.
    P. Agrawal and V.D. Agrawal, “Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Networks,” IEEE Transactions on Computers, vol. C-24, pp. 691–694, July 1975.Google Scholar
  8. 8.
    J.P. Hayes, “A NAND Model for Fault Diagnosis in Combinational Logic Networks,” IEEE Transactions on Computers, vol. C-20, pp. 1491–1506, December 1971.Google Scholar
  9. 9.
    W.H. Kautz, “State-Logic Relations in Autonomous Sequential Networks,” Proc. 1958 Eastern Joint Computer Conference, 1958, pp. 119–127.Google Scholar
  10. 10.
    B. Elspas, “Self-Complementary Symmetry Types of Boolean Functions,” IRE Transactions on Electronic Computers,vol. EC-9, pp. 264–266, June 1960.Google Scholar
  11. 11.
    A. Chatterjee and J.A. Abraham, “Test generation, Design-for-Testability and Built-in Self-Test for Arithmetic Units Based on Graph Labeling,” Journal of Electronic Testing: Theory and Applications, vol. 2, pp. 351–372, December 1991.Google Scholar
  12. 12.
    S. Kundu, “Basis Sets for Synthesis of Switching Functions,” IEEE Transactions on Computers, vol. 41, pp. 489–493, April 1992.Google Scholar
  13. 13.
    S.B. Akers, “A Parity Bit Signature for Exhaustive Testing,” IEEE Transactions on Computer-Aided Design, vol. 7, pp. 333–338, March 1988.Google Scholar
  14. 14.
    C.-I.H. Chen and J.T. Yuen, “Automated Synthesis of Pseudo-Exhaustive Test Generator in VLSI BIST Design. BIST Design,” IEEE Transactions on VLSI Systems, vol. 3, pp. 273–291, September 1994.Google Scholar
  15. 15.
    D. Kagaris, F. Makedon, and S. Tragoudas, “A Method for Pseudo-Exhaustive Test Pattern Generation,” IEEE Transactions on Computer-Aided Design, vol. 13, pp. 1170–1178, September 1994.Google Scholar
  16. 16.
    R. Srinivasan, S.K. Gupta, and M.A. Breuer, “An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing,” Proc. 1993 Design Automation Conference, 1993, pp. 242–248.Google Scholar
  17. 17.
    K. Chakrabarty and J.P. Hayes, “Efficient Test Response Compression for Multiple-Output Circuits,” Proc. 1994 Int. Test Conference, 1994, pp. 501–510.Google Scholar
  18. 18.
    Y. Zorian and A. Ivanov, “Programmable Space Compaction for BIST,” Proc. 1993 Int. Symp. on Fault-Tolerant Computing, 1993, pp. 340–349.Google Scholar
  19. 19.
    Y. You and J.P. Hayes, “Implementation of VLSI Self-Testing by Regularization,” IEEE Transactions on Computer-Aided Design, vol. 8, pp. 1261–1271, December 1988.Google Scholar
  20. 20.
    F. Brglez and H. Fujiwara, “A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Simulator in Fortran,” Proc. 1985 Int. Symp. on Circuits and Systems, 1985, pp. 695–698.Google Scholar
  21. 21.
    Texas Instruments, The TTL Data Book, vol. 2. Dallas, 1988.Google Scholar
  22. 22.
    W.H. McAnney and J. Savir, “Built-in Checking of the Correct Self-Test Signature,” IEEE Transactions on Computers, vol. 37, pp. 1142–1145, September 1988.Google Scholar
  23. 23.
    J.P. Hayes and A.D. Friedman, “Test Point Placement to Simplify Fault Detection,” IEEE Transactions on Computers, vol. C-33, pp. 727–735, July 1974.Google Scholar
  24. 24.
    I. Pomeranz, L.N. Reddy, and S.M. Reddy, “COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits,” Proc. 1991 Int. Test Conference, 1991, pp. 194–203.Google Scholar
  25. 25.
    H.K. Lee and D.S. Ha. On the Generation of Test Patterns for Combinational Circuits. Technical Report No. 12-93, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University.Google Scholar
  26. 26.
    S.M. Reddy, K.K. Saluja, and M.G. Karpovsky, “A Data Compression Technique for Built-in Self-Test,” IEEE Transactions on Computers, vol. C-37, pp. 1151–1156, September 1988.Google Scholar
  27. 27.
    H. Fujiwara and A. Yamamoto, “Parity-Scan Design to Reduce the Cost of Test Application,” IEEE Transactions on Computer-Aided Design, vol. 12, pp. 1604–1611, October 1993.Google Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Krishnendu Chakrabarty
    • 1
  • John P. Hayes
    • 2
  1. 1.Department of Electrical, Computer and Systems EngineeringBoston UniversityBostonUSA
  2. 2.Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn ArborUSA

Personalised recommendations