Abstract
In this work, we present the results of an investigation of the impact of the stress on a poly-silicon channel induced by the neighboring layers in three-dimensional vertical NAND (3D V-NAND) flash memories. Using 3D process simulations, we confirmed the distributions of the residual stress after each process step in the cross-section of a NAND flash unit cell. To investigate the impact of the stress on the poly-silicon channel, we also studied the residual stress after changing the intrinsic stresses of the oxide-nitride-oxide (ONO) layer and the tungsten layer used as a gate. We found that the amplitude of the residual stress in the applied layer became larger as the intrinsic stress increased. In addition, the intrinsic tensile/compressive stresses in the outer layers affected the residual stresses of the previously deposited layers in an opposite nature of the stresses. The cylindrical poly-silicon channel was influenced by the intrinsic stresses of the oxide layers adjacent to the nitride and the tungsten films, with the intrinsic stress of the tunnel oxide having the greater effect on the residual stress in the channel. Because such stresses affect the electrical properties of the devices, optimized deposition conditions are required to control them. Such conditions would aid in improving the performances of 3D NAND flash memories.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata et al., in Proceedings of the 2007 IEEE Symposium on VLSI Technology (Kyoto, Japan, June 12 - 14, 2007), p. 14.
Y. H. Hsiao, H. T. Lue, W. C. Chen, C. P. Chen, K. P. Chang, Y. H. Shih, B. Y. Tsui and C. Y. Lu, in Proceedings of the 2012 IEEE International Electron Devices Meeting (San Francisco, CA, USA, December 10 - 13, 2012), p. 26.7.1.
S. M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son et al., in Proceedings of the 2006 IEEE International Electron Devices Meeting (San Francisco, CA, USA, December 11 - 13, 2006), p. 1.
J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J. H. Jeong, B. K. Son et al., in Proceedings of the 2009 IEEE Symposium on VLSI Technology (Kyoto, Japan, June 15 - 17, 2009), p. 192.
W. Cho, S. I. Shim, J. Jang, H. Cho, B. K. You, B. K. Son, K. Kim, J. J. Shim, C. Park et al., in Proceedings of the 2010 IEEE Symposium on VLSI Technology (Honolulu, Hawaii, USA, June 15 - 17, 2010), p. 173.
D. Kang, W. Jeong, C. Kim, D. H. Kim, Y. S. Cho, K. T. Kang, J. Ryu, K. M. Kang, S. Lee et al., in Proceedings of the 2016 IEEE International Solid-State Circuits Conference (San Francisco, CA, USA, January 31 - February 4, 2016), p. 130.
N. Serra and D. Esseni, IEEE Trans. Electron Devices 57, 482 (2010).
S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass et al., IEEE Trans. Electron Devices 51, 1790 (2004).
S. E. Thompson, G. Sun, Y. S. Choi and T. Nishida, IEEE Trans. Electron Devices 53, 1010 (2006).
P. K. Nag, K. Tripathi and C. B. Pawar, Basic Mechanical Engineering (BE 204) (Tata McGraw-Hill, New Delhi, 2009), p. 1.2.
M. Ohring, Material Science of Thin Films, Deposition and Structure, 2nd ed. (Academic Press, San Diego, CA, 2002), p. 405.
Synopsys Inc., SentaurusTM Process User Guide K-2015.06 (Synopsys Inc., Mountain View, CA, 2015), p. 1.
M. T. Kim, Thin Solid Films 283, 12 (1996).
H. O. Pierson, Handbook of Chemical Vapor Deposition (CVD), Second Edition (Noyes Publications, Norwich, New York, 1999), p. 281.
R. Vepa, Dynamics of Smart Structures (Wiley, Chichester, 2010), p. 141.
W. N. Sharpe, Jr., Springer Handbook of Experimental Solid Mechanics (Springer, New York, 2008), p. 207.
K. W. Ang, K. J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M. F. Li, G. Samudra and Y. C. Yeo, in Proceedings of the 2004 IEEE International Electron Devices Meeting (San Francisco, CA, USA, December 13 - 15, 2004), p. 1069.
R. F. Wolffenbuttel, Silicon Sensors and Circuits: On-Chip Compatibility (Springer, The Netherlands, 1995), p. 131.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Kim, KB., Oh, YT. & Song, YH. Simulation of residual stress and its impact on a poly-silicon channel for three-dimensional, stacked, vertical-NAND flash memories. Journal of the Korean Physical Society 70, 1041–1048 (2017). https://doi.org/10.3938/jkps.70.1041
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.3938/jkps.70.1041