Abstract
A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3Vinterface.Anew level converter realized with +1.8Vdevices that can convert 0/1Vvoltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.
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Original Russian Text © B. Mahendranath, A. Srinivasulu, 2017, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Radioelektronika, 2017, Vol. 60, No. 11, pp. 663–672.
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Mahendranath, B., Srinivasulu, A. Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology. Radioelectron.Commun.Syst. 60, 512–518 (2017). https://doi.org/10.3103/S0735272717110061
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DOI: https://doi.org/10.3103/S0735272717110061