Skip to main content
SpringerLink
Log in

Organization of a Fully Self-Checking Structure of a Combinational Device Based on Searching for Groups of Symmetrically Independent Outputs

  • Published:
Automatic Control and Computer Sciences Aims and scope Submit manuscript

Abstract

A new technique is elaborated for building combinational devices with fully self-checking structures, where any kind of single stuck-at faults in internal logical elements is detected. The suggested technique is based on searching for groups of combinational device outputs in which symmetrical errors are impossible (SI groups). When establishing such groups, the developer can choose the implementation options for a self-checking device, each of which assumes the use of a code for failure control with the detection of any unidirectional and asymmetrical errors (identified multiplicities included).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.

Similar content being viewed by others

REFERENCES

  1. Sogomonyan, E.S. and Slabakov, E.V., Samoproveryaemye ustroistva i otkazoustoichivye sistemy (Self-Checking Devices and Fault-Tolerant Systems), Moscow: Radio i Svyaz’, 1989.

  2. Parkhomenko, P.P. and Sogomonyan, E.S., Osnovy tekhnicheskoi diagnostiki (optimizatsiya algoritmov diagnostirovaniya, apparaturnye sredstva) (Fundamentals of Technical Diagnostics (Optimization of Diagnostic Algorithms and Hardware)), Moscow: Energoatomizdat, 1981.

  3. Lala, P.K., Self-Checking and Fault-Tolerant Digital Design, San Francisco: Morgan Kaufmann Publishers, 2001.

    Google Scholar 

  4. Fujiwara, E., Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons, 2006.

    Book  Google Scholar 

  5. Goessel, M., Ocheretny, V., Sogomonyan, E., and Marienfeld, D., New Methods of Concurrent Checking: Edition 1, Dordrecht: Springer Science+Business Media B.V., 2008.

  6. Stempkovskii, A.L., Tel’pukhov, D.V., Demeneva, A.I., and Zhukova, T.D., Route of designing functional control schemes for combinational devices, Vestn. Ryazan. Gos. Radiotekh. Univ., 2018, no. 65, pp. 92–98.

  7. Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Kody Khemminga v sistemakh funktsional’nogo kontrolya logicheskikh ustroistv (Hamming Codes in Systems of Functional Control of Logical Devices), St. Petersburg: Nauka, 2018.

    Google Scholar 

  8. Nicolaidis, M. and Zorian, Y., On-line testing for VLSI—A compendium of approaches, J. Electron. Test.: Theory Appl., 1998, vol. 12, nos. 1–2, pp. 7–20.

    Article  Google Scholar 

  9. Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Classification of errors in data vectors of systematic codes, Izv. Vuzov,Priborostr., 2015, vol. 58, no. 5, pp. 333–343.

    Google Scholar 

  10. Goessel, M., Morozov, A.A., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Investigation of combination self-testing devices having independent and monotone independent outputs, Autom. Remote Control, 1997, vol. 58, no. 2, pp. 299–309.

    MATH  Google Scholar 

  11. Saposhnikov, V.V., Morosov, A., Saposhnikov, Vl.V., and Goessel, M., A new design method for self-checking unidirectional combinational circuits, J. Electron. Test.: Theory Appl., 1998, vol. 12, nos. 1–2, pp. 41–53.

    Article  Google Scholar 

  12. Morosow, A., Saposhnikov, V.V., Saposhnikov, Vl.V., and Goessel, M., Self-checking combinational circuits with unidirectionally independent outputs, VLSI Des., 1998, vol. 5, no. 4, pp. 333–345.

    Article  Google Scholar 

  13. Goessel, M. and Sogomonyan, E.S., Formation of self-testing and self-checking combinational circuits with weakly independent outputs, Autom. Remote Control, 1992, vol. 53, no. 8, pp. 1264–1272.

    MATH  Google Scholar 

  14. Sogomonyan, E.S. and Gössel, M., Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs, J. Electron. Test.: Theory Appl., 1993, vol. 4, no. 4, pp. 267–281.

    Article  Google Scholar 

  15. Busaba, F.Y. and Lala, P.K., Self-checking combinational circuit design for single and unidirectional multibit errors, J. Electron. Test.: Theory Appl., 1994, vol. 5, no. 5, pp. 19–28.

    Article  Google Scholar 

  16. Matrosova, A.Yu., Levin, I., and Ostanin, S.A., Self-checking synchronous FSM network design with low overhead, VLSI Des., 2000, vol. 11, no. 1, pp. 47–58.

    Article  Google Scholar 

  17. Matrosova, A., Levin, I., and Ostanin, S., Survivable self-checking sequential circuits, Proceedings of 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001), San Francisco, 2001, pp. 395–402.

  18. Matrosova, A. and Mitrofanov, E., Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults, Proceedings of 14th IEEE East-West Design & Test Symposium (EWDTS’2016), Yerevan, 2016, pp. 533–536.

  19. Ostanin, S., Self-checking synchronous FSM network design for path delay faults, Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTS’2017), Novi Sad, 2017, pp. 696–699.

  20. Piestrak, S.J., Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wrocław: Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995.

    Google Scholar 

  21. Ubar, R., Raik, J., and Vierhaus, H.-T., Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source), New York: IGI Global, 2011.

    Book  Google Scholar 

  22. Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger’s Code, Autom. Remote Control, 2017, vol. 78, no. 5, pp. 892–902.

    Article  Google Scholar 

  23. Berger, J.M., A note on error detecting codes for asymmetric channels, Inf. Control, 1961, vol. 4, no. 1, pp. 68–73.

    Article  Google Scholar 

  24. Das, D. and Touba, N.A., Weight-based codes and their application to concurrent error detection of multilevel circuits, Proceedings of 17th IEEE Test Symposium, 1999, pp. 370–376.

  25. Sapozhnikov, V.V., Sapozhnikov, Vl.V., and Efanov, D.V., Weighted codes with summation for control of logical devices, Elektron. Model., 2014, vol. 36, no. 1, pp. 59–80.

    Google Scholar 

  26. Sapozhnikov, V., Sapozhnikov, Vl., Efanov, D., and Nikitin, D., Combinational circuits checking on the base of sum codes with one weighted data bit, Proceedings of 12th IEEE East-West Design & Test Symposium (EWDTS’2014), Kyiv, 2014, pp. 126–136.

  27. Freiman, C.V., Optimal error detection codes for completely asymmetric binary channels, Inf. Control, 1962, vol. 5, no. 1, pp. 64–71.

    Article  MathSciNet  Google Scholar 

  28. Efanov, D.V., Sapozhnikov, V.V., and Sapozhnikov, Vl.V., Sum codes with fixed values of multiplicities for detectable unidirectional and asymmetrical errors for technical diagnostics of discrete systems, Autom. Remote Control, 2019, vol. 80, no. 6, pp. 1082–1097.

    Article  MathSciNet  Google Scholar 

  29. Mitra, S. and McCluskey, E.J., Which concurrent error detection scheme to choose?, Proceedings of International Test Conference, 2000, pp. 985–994.

  30. Ghosh, S., Basu, S., and Touba, N.A., Synthesis of low power CED circuits based on parity codes, Proceedings of 23rd IEEE VLSI Test Symposium (VTS’05), 2005, pp. 315–320.

  31. Sapozhnikov, V.V., Sapozhnikov, Vl.V., Efanov, D.V., and Dmitriev, V.V., New structures of the concurrent error detection systems for logic circuits, Autom. Remote Control, 2017, vol. 78, no. 2, pp. 300–313.

    Article  MathSciNet  Google Scholar 

  32. Borecký, J., Kohlík, M., and Kubátová, H., Parity driven reconfigurable duplex system, Microprocess. Microsyst., 2017, vol. 52, pp. 251–260.

    Article  Google Scholar 

  33. Sapozhnikov, V., Sapozhnikov, Vl., and Efanov, D., Search algorithm for fully tested elements in combinational circuits, controlled on the basis of Berger codes, Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTS’2017), Novi Sad, 2017, pp.99–108.

Download references

Author information

Authors and Affiliations

  1. Russian University of Transport, 127994, Moscow, Russia

    D. V. Efanov

  2. Emperor Alexander I St. Petersburg State Transport University, 190031, St. Petersburg, Russia

    V. V. Sapozhnikov & Vl. V. Sapozhnikov

Authors
  1. D. V. Efanov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. V. V. Sapozhnikov
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Vl. V. Sapozhnikov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to D. V. Efanov or Vl. V. Sapozhnikov.

Ethics declarations

The authors declare that they do not have a conflict of interest.

Additional information

Translated by S. Kuznetsov

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Efanov, D.V., Sapozhnikov, V.V. & Sapozhnikov, V.V. Organization of a Fully Self-Checking Structure of a Combinational Device Based on Searching for Groups of Symmetrically Independent Outputs. Aut. Control Comp. Sci. 54, 279–290 (2020). https://doi.org/10.3103/S0146411620040045

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.3103/S0146411620040045

Keywords:

Search

Navigation