The Formation of Nano-voids in electroless Cu Layers

Abstract

The electrical reliability of multilayer high density interconnection printed circuit boards (HDI-PCBs) is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. In this paper we will show that state-of-the-art electroless Cu plating processes are able to provide solid, completely recrystallized and highly reliable stacked via junctions. Defect free interfaces were achieved by using ionic Pd-activators and electroless Cu baths with a cyanide based stabilizer system. Cyanide free electroless Cu baths tend more to the formation of nanometer sized defects, discovered via Transmission Electron Microscopy (TEM). In this case a precise adjustment of single stabilizer components is mandatory to achieve defect free layers. The defects are hollow and were identified as “nano voids”. A critical density of these nano voids weakens the interface, predefines the crack path and reduces the overall reliability of the junction. A precise localization of the nano voids within the junction was enabled by detecting the Ni-containing electroless Cu layer via TEM-Ni mapping. Slower volume exchange of the electroless Cu solution within the blind micro via (BMV) substantially increases the nano void density. The ability of nano voids to migrate and coalesce at elevated temperatures was investigated as well.