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Parallel Programming

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Abstract

The genesis of parallel programming models is considered. It is shown that parallelism and hardware support of synchronization inherent in an architecture determine a parallel programming model. Modern VLSI technology require shift to programming models based on shared memory.

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REFERENCES

  1. Evreinov, E.V. and Kosarev, Yu.G., Odnorodnye universal’nye vychislitel’nye sistemy vysokoi proizvoditel’nosti (Homogeneous Universal High-Performance Computing Systems), Novosibirsk: Nauka, 1966.

  2. Fortov, V.E., Levin, V.K., Savin, G.I., Zabrodin, A.V., Karatanov, V.V., Elizarov, G.S., Korneev, V.V., and Shabanov, B.M., The MVS-1000M supercomputer and its application prospects, Nauka Prom. Ross., 2001, vol. 55, no. 11, p. 49.

    Google Scholar 

  3. Korneev, V.V., Arkhitektura vychislitel’nykh sistem s programmiruemoi strukturoi (Architecture of Computer Systems with Programmable Structure), Novosibirsk: Nauka, 1985.

  4. Besta, M. and Hoefler, T., Slim Fly: A cost effective low-diameter network topology, Proc. Int. Conf. High Performance Computing, Networking, Storage, and Analysis, New Orleans, 2014, pp. 348–359.

  5. Deng, Y., Guo, M., Ramos, A.F., Huang, X., Xu, Zh., and Liu, W., Optimal low-latency network topologies for cluster performance enhancement.

  6. Wheeler, K., et al., Qthreads: An API for programming with millions of lightweight threads, Proc. Workshop Multithreaded Architectures and Applications at IEEE IPDPS, 2008.

  7. Korneev, V.V., An approach to programming supercomputers based on multicore multithreaded VLSI chips, Vychisl. Metody Program., 2009, vol. 10, pp. 123–128.

    Google Scholar 

  8. Wen, X. and Vishkin, U., FPGA-based prototype of a PRAM-on-chip processor, Proc. 5th Conf. Computing Frontiers Pages, New York, 2008, pp. 55–66.

  9. Elizarov, S.G., Luk’yanchenko, G.A., and Korneev, V.V., Technology of parallel programming of exaflops computers, Program. Inzh., 2015, no. 7, pp. 3–10.

  10. Institute of Electrical and Electronics Engineers, Portable Operating Systems Interface (POSIX.1), 1990. https://nvlpubs.nist.gov/nistpubs/Legacy/FIPS/fipspub151-2.pdf.

  11. Feo, J., Dataflow on Cray XMT. https://www.youtube.com/watch?v=5nj1Ql0Eo5k&t=1266s.

  12. Korneev, V.V., Programming model: Paradigm shift, Otkrytye Sist., 2010, no. 3, pp. 29–31.

  13. Korneev, V.V., Programming model and architecture of an exaflop supercomputer, Otkrytye Sist., 2014, no. 10, pp. 20–22.

  14. Torii, S. and Ishikawa, H., ZettaScaler: Liquid immersion cooling manycore based supercomputer, 2017.

  15. Jia, Zh., Tillman, B., Maggioni, M., and Scarpazza, D., Dissecting the graphcore IPU architecture via microbenchmarking, 2019.

  16. Gurd, J., Bohm, W., and Teo, Y., Performance issues in dataflow machines, Future Gener. Comput. Syst., 1987, pp. 285–297.

  17. Burtsev, V.S., The choice of a new system for organizing the execution of highly parallel computing processes, examples of possible architectural solutions for building supercomputers, Parallelizm vychislitel’nykh protsessov i razvitie arkhitektury SuperEVM (Parallelism of Computing Processes and Development of Supercomputer Architecture), 1997, pp. 41–78.

  18. Klimov, A.V., Levchenko, N.N., and Okunev, A.S., Advantages of a data flow computing model in heterogeneous networks, Inf. Tekhnol. Vychisl. Sist., 2012, no. 2, pp. 36–45.

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Authors and Affiliations

  1. Research and Development Institute ‘Kvant’, 4-i Likhachevskii per. 15, 125438, Moscow, Russia

    V. V. Korneev

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  1. V. V. Korneev
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Correspondence to V. V. Korneev.

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Translated by Yu. Kornienko

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Korneev, V.V. Parallel Programming. Program Comput Soft 49, 310–324 (2023). https://doi.org/10.1134/S0361768823040084

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  • DOI: https://doi.org/10.1134/S0361768823040084

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