Introduction

Two-dimensional (2D) semiconducting materials beyond graphene1,2 are receiving increasing attention owing to their ultra-thin body nature that can mitigate detrimental short-channel effects in aggressively scaled devices through improved electrostatics, enabling them to replace or complement the aging Si technology3,4,5. Molybdenum disulfide (MoS2) and tungsten disulfide (WS2), belonging to the family of transition metal dichalcogenides (TMDs), have been studied extensively in this context. In fact, high performance MoS2 field-effect transistors (FETs) with a contact pitch of 70 nm and 42 nm have already been experimentally demonstrated6,7. Circuit level implementations of 2D FETs such as inverters, logic operators, ring oscillators, and radio-frequency devices have also been achieved8,9,10,11,12. Recently, a microprocessor based on MoS2 FETs was reported13. Additionally, 2D FETs have found applications in various emerging technologies such as sensors for internet of things, neuromorphic computing, biomimetic devices, valleytronics, straintronics, and optoelectronic devices14,15,16,17,18,19,20,21. While initial demonstrations of prototype devices relied on exfoliated flakes, the 2D community has rapidly transitioned towards the growth of large-area films to address manufacturing needs for any commercial applications. In this context, chemical vapor deposition (CVD)22,23 and metal-organic CVD (MOCVD)7,24 are the most promising techniques, enabling growth of high quality 2D materials with different thermal budgets on various substrates. In fact, there are several reports demonstrating high-performance FETs based on CVD and MOCVD grown monolayer MoS2 and WS2. However, most of these studies are based on one or only a few devices.

To assess the potential of 2D materials for future very large scale integrated (VLSI) circuits, it is important to study the variation in key device parameters that determine the ON-state and OFF-state performance across a large number of devices. Unfortunately, there are only a few studies that report device-to-device variation in 2D FETs7,25,26. Smithe et al. measured multiple parameters across 200 MoS2 FETs and demonstrated low threshold voltage variation and low contact resistance on the order of 1 kΩ−μm25. Similarly. Xu et al. analyzed 380 top-gated MoS2 FETs and reported variation in threshold voltage and electron mobility26. However, both works concentrate on longer channel devices where the effects of contact resistance are not pronounced. In a separate study, Smithe et al.22 measured scaled MoS2 FETs based on synthetic monolayers; however, they did not provide any statistics. Smets et al.7 demonstrated the most significant study on scaling of CVD grown monolayer MoS2, wherein multiple devices with channel lengths ranging from 5 μm down to 29 nm were measured. However, their study was focused on the OFF-state performance. Finally, all of the aforementioned studies are based on MoS2 FETs, and none exist for WS2 FETs.

This work focuses on a comprehensive study of variation in key parameters related to both OFF-state and ON-state performance, such as threshold voltage, subthreshold slope, ratio of maximum to minimum current, field-effect carrier mobility, contact resistance, drive-current, and carrier saturation velocity, for different channel lengths ranging from 5 μm down to 100 nm using 230 MoS2 FETs and 160 WS2 FETs. In addition, we offer extensive benchmarking of our devices with respect to the above-mentioned demonstrations as well as ultra-thin body (UTB) silicon (Si) on insulator (SOI) FETs with similar gate lengths to assess the technological viability and maturity of 2D FETs. Using statistical measures such as mean, median, standard deviation, and minimum/maximum values, we show low device-to-device variation. We are also able to demonstrate record high carrier mobility of 33 cm2 V−1 s−1 in WS2 FETs, which is a 1.5X improvement compared to the best reported in the literature. We attribute our accomplishments to the epitaxial growth of highly crystalline 2D monolayers on sapphire substrate via MOCVD technique at 1000 °C using chalcogen and sulfur precursors that minimize carbon contamination in the film, as well as to the clean transfer of the film from the growth substrate to the device fabrication substrate.

Results

Synthesis and characterization of monolayer MoS2 and WS2

MoS2 and WS2 were deposited by MOCVD on epi-ready 2″ diameter c-plane sapphire wafers. Figure 1 summarizes the growth, structural, and optical characterization of the MOCVD grown MoS2 and WS2. Figure 1a shows the schematic of the MOCVD system, comprising of a cold-wall horizontal reactor with an inductively heated graphite susceptor equipped with wafer rotation as previously described27. Molybdenum hexacarbonyl (Mo(CO)6) and tungsten hexacarbonyl (W(CO)6) were used as metal precursors, while hydrogen sulfide (H2S) was the chalcogen source with H2 as the carrier gas. MoS2 was deposited in a single step process at 1000 °C, where coalesced monolayer growth across the 2″ wafer was achieved in 18 min. WS2 was deposited using a multi-step process with nucleation at 850 °C and lateral growth at 1000 °C, resulting in coalesced monolayer growth across the 2″ wafer in 10 min28. In both cases, after growth the substrate was cooled in H2S to 300 °C to inhibit decomposition of the MoS2 and WS2 films. Figure 1b shows uniformly grown MoS2 and WS2 films over 2″ sapphire wafers. Further growth details can be found in the “Methods” section. The morphology of the monolayer films at the center and edge of the 2″ wafer is shown in Fig. 1c, d for MoS2 and WS2, respectively, using atomic force microscopy (AFM). Height profiles obtained from scratch testing confirm monolayer film formation (see Supplementary Fig. 1a, b). The monolayers are fully coalesced, with undulations arising from steps on the sapphire surface. The overall bilayer density is low but a higher density of bilayers is present at the center of the MoS2 film compared to the WS2 film. The in-plane X-ray diffraction (XRD) patterns in Fig. 1e, f highlight the epitaxial relation between the sulfide monolayers and the underlying sapphire substrates. The full-width at half maxima of the ϕ-scan peaks are 0.3° and 0.17° for MoS2 and WS2, respectively, indicating a low rotational misorientation of domains within the monolayers. The films were transferred to Al2O3/Pt/TiN/p++-Si substrates for device fabrication, as discussed later. The transferred film quality was assessed using Raman maps as shown in Fig. 1g, h, and photoluminescence (PL) maps as shown in Fig. 1i, j, for MoS2 and WS2, respectively. Raman maps show less than 5% variation in the representative A1g peak position. The uniform PL peak positions observed at 1.84 eV for MoS2 and 1.97 eV for WS2 correspond to their monolayer response. Representative Raman and PL spectra are included in the Supplementary Fig. 1c–f.

Fig. 1: Monolayer film growth and characterization.
figure 1

a Schematic of the MOCVD system with a cold-wall horizontal reactor. b 2″ sapphire wafer with MOCVD grown MoS2 and WS2. AFM images of c MoS2 and d WS2 at the center and edge of the respective wafers. Towards the center of the MoS2 film, few bilayers are seen. In-plane XRD ϕ-scan of e MoS2 and f WS2 on sapphire (α-Al2O3), showing the epitaxial relationship between the monolayers and the sapphire substrate. Raman map of the A1g peak position for g MoS2 and h WS2 films transferred from the growth substrate onto the device fabrication substrate with 50 nm ALD Al2O3. Low variation in the peak position is observed for both MoS2 and WS2 with an average of ≈403.5 cm−1 and ≈417 cm−1, respectively. PL peak map of i MoS2 with an average of ≈1.85 eV and j WS2 with an average of ≈1.97 eV, confirm monolayer films. PL is a characteristic of monolayer film owing to indirect to direct bandgap transition.

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Monolayer MoS2 and WS2 device fabrication and characterization

To investigate the electrical properties of the MOCVD grown TMD films, back-gated FETs were fabricated on Al2O3/Pt/TiN/p++-Si substrates. 50 nm Al2O3 gate dielectric was deposited using atomic layer deposition (ALD). The choice of a thin, high-k gate dielectric with an effective oxide thickness (EOT) of 22 nm, compared to conventionally used 300 nm SiO2, was to allow for better gate electrostatics. The Pt/TiN/ p++-Si stack acts as the gate electrode (see “Methods” section for more details on gate dielectric fabrication) for each substrate. The TMD films were transferred from sapphire (growth substrates) onto the Al2O3 substrates via the poly(methyl methacrylate) (PMMA)-assisted wet-transfer process29, as shown in Fig. 2a (see “Methods” section for more details on transfer of monolayer films). Following transfer, electron beam (e-beam) lithography and dry etching using SF6 plasma were used to isolate the channel area of each device. Next, transmission line measurement (TLM) structures were defined using another set of e-beam exposures. Finally, e-beam evaporation was performed to sequentially deposit 40 nm Ni and 30 nm Au to serve as the contacts for the FETs (see “Methods” section for more details on device fabrication). The TLM structures were designed to have channel lengths (LCH) of 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm, while the channel width (W) was kept constant at 5 μm. Figure 2b, c, respectively, show the schematic and scanning electron microscope (SEM) image of the fabricated TLM structures. Figure 2d–g show the transfer characteristics, i.e., drain current (IDS) versus gate voltage (VGS), for different drain voltages (VDS) in linear and logarithmic scales for representative longest-channel length (LCH = 5 μm) and shortest-channel length (LCH = 100 nm) FETs, for both MoS2 and WS2. Strong n-type conduction is observed due to Fermi-level pinning of the contact metal close to the conduction band of both MoS2 and WS230. Figure 2h–k show the corresponding output characteristics, i.e., IDS versus VDS, for different VGS. Measurement protocols are described in the “Methods” section.

Fig. 2: Device fabrication and electrical measurements.
figure 2

a Schematic representation of PMMA-assisted wet transfer of monolayer TMD films from sapphire (growth substrate) to an Al2O3 substrate. b Schematic representation and c SEM of a TLM structure defined using e-beam lithography. TLM structures with channel length (LCH) from 100 nm to 5 μm are fabricated and the channel width is defined to be 5 μm. Transfer characteristics, i.e., drain current (IDS) versus gate voltage (VGS), for different drain voltages (VDS) in logarithmic and linear scale for d longest-channel (LCH = 5 μm) and e shortest-channel (LCH = 100 nm) MoS2 field-effect transistors (FETs), and f longest-channel (LCH = 5 μm) and g shortest-channel (LCH = 100 nm) WS2 FETs. Corresponding output characteristics, i.e., IDS versus VDS, for different VGS for h longest-channel and i shortest-channel MoS2 FETs, and j longest-channel and k shortest-channel WS2 FETs.

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Device-to-device variation in monolayer MoS2 and WS2 FETs

To understand the variation in the FET performance across the entire 1 × 1 cm2 substrates, as well as to study of the impact of channel length scaling on FET performance, 230 MoS2 FETs (23 TLM structures) and 160 WS2 FETs (16 TLM structures) were measured. Figure 3a, b display the transfer characteristics of all measured MoS2 and WS2 FETs, respectively, for different LCH, which were used to extract key device parameters. For each parameter, the mean, median, standard deviation, minimum, and maximum values are reported. Finally, median values are used for benchmarking since they reflect the central tendency, even in the presence of outliers in the data, and offer higher accuracy in case of skewed distributions. Devices with the best number for a given parameter are termed as “champion” devices.

Fig. 3: Statistics of scaled devices.
figure 3

A total of 230 MoS2 FETs and 160 WS2 FETs were fabricated using 23 and 16 TLM structures with channel lengths ranging from LCH = 100 nm to LCH = 5 μm for a MoS2 and b WS2, respectively, to analyze the device-to-device variation and impact of scaling on the device performance. The corresponding transfer characteristics, i.e., IDS versus VGS, for VDS of 1 V are shown in the logarithmic scale.

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Threshold voltage

Threshold voltage is extracted using three different methods: linear extrapolation (\(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\)), Y-function (\(V_{{\mathrm{t}}_Y}\)), and constant-current method (\(V_{{\mathrm{t}}_{{\mathrm{cc}}}}\)). Supplementary Fig. 2a–c describes the extraction of \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\), \(V_{{\mathrm{t}}_Y}\), and \(V_{{\mathrm{t}}_{{\mathrm{cc}}}}\), Supplementary Fig. 2d, e show their corresponding median values as a function of LCH, and Supplementary Fig. 2f, g show their distributions across all devices for MoS2 and WS2, respectively. Supplementary Note 1 and Supplementary Table 1 summarize the device-to-device variations. It was found that the threshold voltage is independent of the channel length for both MoS2 and WS2 FETs. Figure 4a, b show the distributions of \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) for all measured MoS2 and WS2 FETs, respectively. Median \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) of 2.9 V with a standard deviation of \(\sigma _{V_{\mathrm{t}}}\) = 0.8 V is obtained for MoS2, and median \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) of 6.4 V with a \(\sigma _{V_{\mathrm{t}}}\) = 0.8 V is obtained for WS2. Threshold voltage was found to be more positive for WS2 FETs compared to MoS2 FETs, which can be attributed to higher intrinsic n-type doping of MoS2 either due to the specific nature of the impurity present in the MOCVD grown MoS2 film or due to surface charge transfer induced doping due to the underlying ALD grown Al2O3. This charge transfer is accredited to the higher conduction band offset between MoS2 and Al2O3 compared to WS2 and Al2O331.

Fig. 4: Variation in OFF-state performance.
figure 4

Histograms showing the variation in threshold voltage extracted using linear extrapolation (Vt,lin) for a MoS2 and b WS2 FETs. The median values for these extracted threshold voltages were found to be more positive for WS2 FETs compared to MoS2 FETs due to higher intrinsic n-type doping of MoS2. Histograms of SS extracted across 4 orders of magnitude change in the drain current (SS4) for c MoS2 and d WS2 FETs. The deviation of SS from the ideal 60 mV.dec−1 corresponds to the presence of interface traps. Histograms of interface trap density (DIT) for e MoS2 and f WS2 FETs calculated from SS4. Histograms of maximum to minimum current ratio (Imax/Imin) for g MoS2 and h WS2 FETs.

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Variation in threshold voltage is widely used for benchmarking emerging devices based on novel materials25. Note that median \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) depends on the work function of the gate metal and unintentional/intrinsic doping of the 2D material and that both \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) and \(\sigma _{V_{\mathrm{t}}}\) depend on the thickness of the gate oxide. Hence for a fair comparison we use \(S\sigma _{V_{\mathrm{t}}}\), which is defined as the projected threshold voltage variation at a scaled effective oxide thickness (SEOT) obtained using Eq. (1). We use SEOT = 0.9 nm for comparison with other literature results.

$$S\sigma _{V_{\mathrm{t}}} = \sigma _{V_{\mathrm{t}}}\frac{{{\mathrm{SEOT}}}}{{{\mathrm{EOT}}}}$$
(1)

This equation assumes linear scaling of variation in threshold voltage with respect to the EOT. However, for ultra-scaled devices, deviation from the linear scaling can be expected due to increased effect of metal-gate granularity32. For our MoS2 and WS2 FETs, we project \(S\sigma _{V_{\mathrm{t}}}\) = 33 mV, which is similar to the value projected for CVD grown monolayer MoS2 FETs reported by Smithe et al.25. We also employed this method to other reports on top-gated and wafer-scale monolayer MoS2 FETs and extracted \(S\sigma _{V_{\mathrm{t}}}\) = 45 mV for26 and \(S\sigma _{V_{\mathrm{t}}}\) = 11 mV for12, respectively. Recently, Smets et al.7 have demonstrated \(\sigma _{V_{\mathrm{t}}}\) = 44 mV for an EOT of 1.9 nm that would correspond to \(S\sigma _{V_{\mathrm{t}}}\) = 20 mV for monolayer MoS2 FETs with channel lengths scaled down to 30 nm. These results are compared with the state-of-the-art UTB SOI and Si FinFET (Table 1). Channel dimensions are included in Table 1 since \(\sigma _{V_{\mathrm{t}}}\) has been found to be inversely proportional to the channel area in ultra-scaled devices which is shown using Pelgrom plots32,33. However, we did not observe such a trend due to relatively large channel areas in our MoS2 and WS2 FETs. It is encouraging that monolayer 2D FETs show \(S\sigma _{V_{\mathrm{t}}}\) comparable to the state-of-the art Si FETs in spite of an order of magnitude smaller body thickness. Note that UTB Si FETs are expected to encounter challenges associated with the precise thickness control, random dopant fluctuations, and detrimental quantum confinement effects beyond 5 nm body thickness34,35, which are unlikely for 2D monolayers. At the same time further improvement in threshold voltage variation can be achieved for 2D FETs through optimization of the monolayer growth and improvement in the fabrication process flow (see Supplementary Note 2 for further discussion). Hence, 2D materials offer an alternative for the realization of UTB MOSFETs. The exhibition of low device-to-device variation in this work, which can be attributed to uniform and contaminant-free MOCVD growth of monolayer TMDs and clean device fabrication process can accelerate the incorporation of 2D FETs in future VLSI technologies.

Table 1 Benchmarking device-to-device variation in threshold voltage.
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Subthreshold slope

Subthreshold slope (SS) is extracted over 1 (SS1), 2 (SS2), 3 (SS3), and 4 (SS4) orders of magnitude change in IDS for MoS2 and WS2 FETs, respectively. Supplementary Fig. 3a, b show the median values for SS1, SS2, SS3, and SS4 as a function of LCH, and Supplementary Fig. 3c, d show the distributions for SS1 and SS4 for all MoS2 and WS2 devices, respectively. Supplementary Table 2 summarizes the device-to-device variation in SS. For a FET with ohmic contacts, it is expected that SS1 = SS2 = SS3 = SS4. However, for a Schottky barrier (SB) FET, the SS may increase when extracted for higher orders of magnitude change in IDS. A greater increase can be attributed to higher SB height at the metal/semiconductor interface, which not only limits the ON-current but also impacts the OFF-state performance. In the existing 2D FET literature there is a tendency to report SS value without mentioning the orders of magnitude change in IDS over which it is evaluated. This leads to considerable discrepancy and unfair comparisons. In fact, most SS values are reported for only one or two orders of magnitude of the drain current, whereas circuit operations require at least four orders of magnitude ON/OFF ratio to be technologically relevant.

We found that the median SS values are independent of LCH for both MoS2 and WS2 FETs (Supplementary Fig. 3a, b). Fig. 4c, d show the distributions of SS4 for all measured MoS2 and WS2 FETs, respectively. A median SS4 of 431.9 mV.dec−1 with a standard deviation of σSS = 138.1 mV.dec−1 is obtained for MoS2, and a median SS4 of 541.4 mV.dec−1 with a σSS = 41.8 mV.dec−1 is obtained for WS2. The median SS4 values show slight increase from the corresponding median SS1 values of 327.1 mV.dec−1 and 438.2 mV.dec−1 for MoS2 and WS2, respectively (Supplementary Table 2). However, no significant difference is found in the standard deviation values for SS1 and SS4. Note that the “champion” MoS2 FET demonstrates SS1 = 93.3 mV.dec−1 and SS4 = 166 mV.dec−1, and the “champion” WS2 FET demonstrates SS1 = 295.6 mV.dec−1 and SS4 = 452.8 mV.dec−1. The deviation of SS from its ideal value of 60 mV.dec−1even for “champion” devices can be explained using Eq. (2).

$${\mathrm{SS}} = \frac{{mk_{\mathrm{B}}T}}{q}{\mathrm{ln}}\left( {10} \right);m = \left( {1 + \frac{{C_{\mathrm{S}}}}{{C_{{\mathrm{OX}}}}} + \frac{{C_{{\mathrm{IT}}}}}{{C_{{\mathrm{OX}}}}}} \right);C_{{\mathrm{IT}}} = qD_{{\mathrm{IT}}}$$
(2)

Here, kB is the Boltzmann constant, T is the temperature, q is the electronic charge, m is the body factor, CS is the semiconductor capacitance, CIT is the interface trap capacitance, COX is the oxide capacitance, and DIT is the interface trap density. For fully depleted UTB FETs such as monolayer MoS2 and WS2 FETs, CS = 0. In case of a clean oxide-semiconductor interface, \(C_{{\mathrm{IT}}} \ll C_{{\mathrm{OX}}}\), ensuring that m = 1 and SS = 60 mV.dec−1. Clearly, in our MoS2 and WS2 FETs, m > 1 indicates the presence of interface traps at the 2D/dielectric interface (finite value of CIT).

Interface traps

To evaluate the quality of the interface, we have extracted DIT using Eq. (2) and the corresponding distributions are shown in Fig. 4e, f for MoS2 and WS2 FETs, respectively. Median DIT of 6.2 × 1012 eV−1 cm−2 and 8 × 1012 eV−1 cm−2 were obtained for MoS2 and WS2, respectively. The device-to-device variation in DIT is shown in Supplementary Table 2. For fully depleted UTB Si MOSFETs with 35 nm thick Si and 110 nm gate length, SS = 80 mV.dec−1 for an EOT = 4 nm, which corresponds to a DIT = 1.5 × 1012 eV−1 cm−236. Note that, while the DIT values for our monolayer 2D FETs are comparable with state-of-the-art Si FETs, thicker EOT = 22 nm results in smaller COX and hence higher median values for the SS for MoS2 and WS2 FETs. For a fair comparison, we project the scaled-SS (SSS) for an EOT of 0.9 nm using the DIT. We found SSS to be 76 mV.dec−1 and 80 mV.dec−1 for MoS2 and WS2, respectively, and 64 mV.dec−1 for the UTB Si MOSFET in ref. 36. A similar exercise was performed for other reports on MoS2 FETs from the literature and the results are summarized in Table 2. The impact of higher DIT at the TMD/Al2O3 interface can be mitigated either by scaling the EOT (i.e., increasing COX)37 or by improving the interface (i.e., reducing DIT). The presence of structural defects such as sulfur vacancies are known to introduce trap sites which contribute to DIT. It has been found that DIT can be reduced by various surface passivation techniques38,39. In addition, photoresist residue from the lithography and/or the wet transfer process can cause an increase in DIT. Therefore it is possible to reduce DIT through further optimization of growth, post-growth processing, and improvement in fabrication process flow.

Table 2 Benchmarking median subthreshold slope for LCH = 100 nm.
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Current ON/OFF ratio

Fig. 4g, h show the distribution of the ratio of maximum to minimum current (Imax/Imin) across all MoS2 and WS2 FETs, respectively. Here, Imax is the maximum current obtained from the transfer characteristics for VDS = 1 V and Imin is the average noise floor. Note that the true device current in the OFF-state is beyond the measurement range of the instrument. See Supplementary Fig. 4a, b for the distribution of Imax and Imin, Supplementary Fig. 4c, d for the distribution of Imax/Imin for different LCH for MoS2 and WS2 FETs, and Supplementary Table 3 for a summary of device-to-device variation in Imax/Imin. The median and standard deviation for Imax/Imin were found to be 2.1 × 107 and 5.5 × 107 for MoS2 FETs and 2.1 × 107 and 2.6 × 107 for WS2 FETs. These values are over an order of magnitude higher than the Imax/Imin of 1.3 × 106 for UTB Si MOSFETs36. Imax/Imin is benchmarked against literature reports for LCH = 100 nm as shown in Supplementary Table 4. Note that the key OFF-state performance indicators, i.e., threshold voltage, SS, DIT, and Imax/Imin, are mostly found to be independent of LCH. Even for LCH = 100 nm, no detrimental short-channel effects are observed, which is expected and can be ascribed to the atomically thin body nature of monolayer TMDs, as well as the use of thin and high-k Al2O3 as the gate dielectric with EOT = 22 nm.

Field-effect mobility and contact resistance

Field-effect mobility (μFE) is an important device parameter that strongly influences the ON-state performance of a FET. While intrinsic mobility is a material related parameter, μFE is determined by extrinsic effects, such as contact resistance (Rc), and often depends on how it is extracted from the device characteristics. Three popular methods for extracting μFE are peak transconductance (\(\mu _{g_{\mathrm{m}}}\)), Y-function (μY)40, and TLM (μTLM) as described in Supplementary Note 3. Figure 5a, b, show the distribution and the corresponding median values for \(\mu _{g_{\mathrm{m}}}\) as a function of LCH for MoS2 and WS2 FETs, respectively. Additionally, 25th and 75th percentile values of the distribution are also marked. Clearly, \(\mu _{g_{\mathrm{m}}}\) shows a strong LCH dependence, with the median value varying from 23.9 cm2 V−1 s−1 to 3.6 cm2 V−1 s−1 for MoS2 and 29 cm2 V−1 s−1 to 2.7 cm2 V−1 s−1 for WS2 as the devices are scaled from LCH = 5 μm down to LCH = 100 nm. Supplementary Fig. 5a, b shows a similar analysis of μY for MoS2 and WS2 FETs, respectively and Supplementary Table 5 summarizes the device-to-device variation in \(\mu _{g_{\mathrm{m}}}\) and μY. Both \(\mu _{g_{\mathrm{m}}}\) and μY extracted from shorter-channel devices show significant reduction in their median values, indicating the dominant role of Rc in scaled 2D FETs6. The contact resistance is seen as a result of Fermi-level pinning at the metal/TMD contact interface, resulting in a finite SB height30. To investigate further, we used the TLM structure shown in Fig. 2c to extract Rc and evaluate its impact on LCH scaling as shown in Fig. 5c–f. We used Eq. (3) to extract Rc.

$$ R_{\mathrm{T}} = 2R_{\mathrm{c}} + R_{{\mathrm{ch}}}; R_{{\mathrm{ch}}} = \frac{{L_{{\mathrm{CH}}}}}{{\mu _{{\mathrm{TLM}}}C_{{\mathrm{OX}}}(V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}})}} = \frac{{L_{{\mathrm{CH}}}}}{{qn_{\mathrm{S}}\mu _{{\mathrm{TLM}}}}}; \\ n_{\mathrm{S}} = \frac{{C_{{\mathrm{OX}}}(V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}})}}{q}$$
(3)

Here, RT is the total measured resistance of the FET, and Rch is the channel resistance, which is directly proportional to LCH and inversely proportional to the carrier density (nS) when the FET is measured in the linear operation regime. However, Rc is independent of LCH and hence can be extracted from the y-intercept of RT versus LCH plots, as shown in Fig. 5c, d for MoS2 and WS2, respectively, for different nS41 (see Supplementary Note 4 for further discussion on the extraction of nS). Figure 5e, f show the distribution of corresponding extracted Rc as a function of nS. A steady decrease in Rc with increasing nS is attributed to the phenomenon of contact-gating in global back-gated FET geometry, since the SB width at the metal/2D interface is modulated by the back-gate voltage30. Lower SB width allows for easier carrier tunneling, reducing Rc. For the MoS2 FET, the median Rc value was found to be 9.2 kΩ−μm, corresponding to nS = 1 × 1013 cm−2. However, for WS2, nS was limited to 4.4 × 1012 cm−2, owing to the more positive \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\), resulting in a higher median Rc = 29.2 kΩ−μm. For a case of identical carrier concentration, nS = 2.7 × 1012 cm−2, similar median Rc values of 33 kΩ−μm and 39.4 kΩ−μm are obtained for MoS2 and WS2, respectively. The difference in Rc between MoS2 and WS2 can be explained from the fact that the charge neutrality level is closer to the conduction band for MoS2 than it is for WS2, resulting in a higher SB height at the Ni/WS2 contact interface compared to the Ni/MoS2 contact interface42.

Fig. 5: Device-to-device variation in field-effect mobility and contact resistance.
figure 5

Distribution of mobility extracted using peak transconductance (\(\mu _{g_{\mathrm{m}}}\)) for different channel lengths for a MoS2 and b WS2 FETs. Median, 25th percentile, and 75th percentile is also denoted. Total resistance (RT) versus LCH for c MoS2 and d WS2 for different carrier concentrations (nS) extracted using a representative TLM structure. The distribution of contact resistance (Rc) across multiple TLM structures, extracted from the y-intercepts in c and d, as a function of nS for e MoS2 and f WS2, respectively. The relative contribution of Rc and channel resistance (Rch) to the total resistance for g MoS2 and h WS2 for different LCH. In scaled devices, as Rch scales with the channel length, the contribution of Rc (note that Rc is independent of LCH), i.e., 2Rc/RT, is more significant compared to Rch, i.e., Rch/RT.

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The relative effect of Rc is assessed for different LCH. Figure 5g, h show the contribution of Rc and Rch to the total resistance RT using stacked bar plots as a function of LCH for MoS2 and WS2, respectively. It is clear that for LCH ≤ 1 μm, the contact effects are significant since 2Rc > Rch. This explains why the extracted \(\mu _{g_{\mathrm{m}}}\) is LCH dependent and is severely underestimated by more than 80% for both MoS2 and WS2 when extracted from scaled devices with LCH = 100 nm. Since \(\mu _{g_{\mathrm{m}}}\) extraction is limited by Rc, extracting μTLM following Eq. (3) is more appropriate for short channel devices. Supplementary Fig. 5c, d show the distribution of μTLM across MoS2 and WS2 TLM structures, respectively, and Supplementary Table 6 summarizes the variation across the different TLM structures. The extracted median value for μTLM was found to be 27 cm2 V−1 s−1 and 16 cm2 V−1 s−1 for MoS2 and WS2 FETs, respectively. Long channel devices are less vulnerable to Rc and corresponding \(\mu _{g_{\mathrm{m}}}\) values are more accurate representations of intrinsic channel mobility, albeit with some challenges as described by Nasr et al.43. Nevertheless, our “champion” long-channel MoS2 and WS2 FETs with LCH = 5 μm demonstrated \(\mu _{g_{\mathrm{m}}}\) = 30 cm2 V−1 s−1 and 33 cm2 V−1 s−1, respectively. Similarly, “champion” MoS2 and WS2 TLM structures demonstrated μTLM = 46 cm2 V−1 s−1 and 33 cm2 V−1 s−1, respectively.

Table 3 shows the benchmarking of our “champion” devices with the best reports from the literature using μFE (\(\mu _{g_{\mathrm{m}}}\) for longer channel devices and μTLM for shorter channel devices) and Rc for both MoS2 and WS2. We have also included median/mean values wherever applicable. Note that while higher μFE values have been reported based on “champion” exfoliated and CVD grown MoS2 FETs7,12,24,25,44,45,46, our report is statistically more significant as it demonstrates variation across multiple TLM structures. For WS2, μFE = 33 cm2 V−1 s−1 is the highest reported, 1.5X better than the previous report on synthetic WS247. Higher μFE values reported for WS2 are either for exfoliated materials at room temperature48 and low temperatures49, or for CVD grown materials with contact engineering via the use of multilayer graphene as interlayers50. More interestingly, UTB Si MOSFETs with 0.9 nm thick Si show μFE ≈ 6 cm2 V−1 s−151, which is more than 2 orders of magnitude smaller compared to bulk Si mobility and is primarily attributed to thickness fluctuation in UTB Si.

Table 3 Benchmarking ON-state performance at VDS = 1 V (best values are compared with median/mean values shown within parentheses).
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Metal/2D contact resistances are comparatively high even for the “champion” devices with Rc = 3 kΩ−μm and Rc = 2.1 kΩ−μm for MoS2 and WS2, respectively, when compared to the Rc = 0.1 kΩ−μm typically reported for state-of-the-art Si FETs. However, various methods have been developed to reduce the effect of SB-limited carrier transport in 2D TMDs52, such as work function engineering to reduce the SB height30, introduction of interlayers such as graphene to decouple the metal/2D interface to alleviate Fermi-level pinning53,54, and achieving higher carrier concentration underneath or near the metal/2D contacts through substitutional or surface charge transfer doping to reduce the SB width42,55. Nevertheless, our MOCVD grown monolayer MoS2 FETs demonstrate Rc similar to values reported in the literature7,22,25,56. The “champion” devices are benchmarked in Table 3. To the best of our knowledge, this is the first report of Rc for synthetic WS2. Additionally, our work marks the first study on the extraction of contact resistance from multiple TLM structures for both MoS2 and WS2. Smithe et al.25 have demonstrated a pseudo-TLM analysis where independent devices with different channel lengths and widths were used to extract the distribution of RT. TLM analysis is done on the devices between 10th and 90th percentile25. Our demonstration involves the extraction of contact resistance from separate TLM structures and finding the variation across these TLM structures, and the analysis is not limited to a percentile limit.

Drive-current and saturation velocity

Finally, high performance FETs are benchmarked using the drive current (ION) that is achievable for a given supply voltage (VDS = VDD). Higher values of ION ensure faster circuit operation as the intrinsic delay of a FET is proportional to CVDD/ION, where C is the load capacitance. In digital electronics, higher ION allows larger fan-out. Figure 6a, b display the output characteristics of MoS2 and WS2 FETs, respectively, for different channel lengths, which were used to assess the ON-state performance of the devices. At high biases, high current density leads to self-heating, resulting in negative differential resistance (NDR) behavior. This is a common phenomenon seen in ultra-thin body FETs, including SOI FETs57, nanowire FETs58, graphene FETs59, and, more recently, exfoliated multilayer MoS2 FETs60 and CVD grown monolayer MoS2 FETs61. It is possible to reduce or eliminate the self-heating effect through pulsed measurements with pulse widths less than 100 μs60.

Fig. 6: ON-state performance of monolayer MoS2 and WS2 FETs.
figure 6

Output characteristics for channel lengths ranging from LCH = 100 nm to LCH = 5 μm, obtained from a representative transmission-line measurement structure for a MoS2 and b WS2 FETs. Current saturation is achieved in shorter-channel devices for both MoS2 and WS2 FETs.

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Figure 7a–d show the median for ION as a function of LCH for VDS = 1 V and VDS = 5 V for MoS2 and WS2 FETs, respectively, extracted from their respective output characteristics. For both TMDs, at low VDS = 1 V, i.e., in the linear region, ION is expected to demonstrate an inverse channel length dependence following Eq. (4).

$$\frac{{I_{{\mathrm{ON}}}}}{W} = \frac{{I_{{\mathrm{DS}},{\mathrm{LIN}}}}}{W} = qn_{\mathrm{S}}\mu _{g_{\mathrm{m}}}\frac{{V_{{\mathrm{DS}}}}}{{L_{{\mathrm{CH}}}}}$$
(4)
Fig. 7: Drive current and saturation velocity.
figure 7

Median of drive current (ION) as a function of 1/LCH for a MoS2 and b WS2 FETs at VDS of 1 V corresponding to the linear region of the FETs, and c MoS2 and d WS2 FETs at VDS of 5 V corresponding to the saturation region of the FETs. These are extracted at carrier concentrations (nS) of 1 × 1013 cm−2 and 4.4 × 1012 cm−2 for MoS2 and WS2, respectively. The saturation current (IDS,SAT) for e MoS2 and f WS2, extracted from their corresponding shorter-channel devices (LCH < 1 μm) as a function of nS. The slope indicates the saturation velocity (vSAT). The distribution of vSAT for g MoS2 and h WS2 shorter-channel FETs.

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This trend is observed for both MoS2 and WS2 FETs in Fig. 7a, b, respectively, for channel lengths LCH ≥ 1 μm. However, for devices with channel length LCH < 1 μm, the inverse channel length dependence is obscured by Rc. Similar linear dependence is observed for ION in longer-channel devices (LCH ≥ 1 μm) at VDS = 5 V for both MoS2 and WS2 FETs in Fig. 7c, d, respectively, following Eq. (5).

$$\frac{{I_{{\mathrm{ON}}}}}{W} = \frac{{I_{{\mathrm{DS}},{\mathrm{SAT}}}}}{W} = \frac{{C_{{\mathrm{OX}}}\mu _{g_{\mathrm{m}}}(V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}})^2}}{{2L_{{\mathrm{CH}}}}} = \frac{{q^2\mu _{g_{\mathrm{m}}}}}{{C_{{\mathrm{OX}}}}}\frac{{n_{\mathrm{S}}^2}}{{2L_{{\mathrm{CH}}}}}$$
(5)

These results are in accordance with classic long-channel FET characteristics (i.e., at low drain bias, the device operates in the linear regime (Eq. (4)), whereas for \(V_{{\mathrm{DS}}} \ge V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}}\), the channel is pinched-off, resulting in current saturation). The saturation current follows a square-law dependence on the overdrive voltage and, therefore, on nS (Eq. (6))62. In shorter-channel devices (LCH < 1 μm), as the lateral electric field (\(\xi \approx \frac{{V_{{\mathrm{DS}}}}}{{L_{{\mathrm{CH}}}}}\)) becomes more than the critical electric field (EC), the carrier velocity reaches saturation velocity (vSAT). This leads to current saturation, with the saturation current being independent of LCH as described by Eq. (6)62.

$$\frac{{I_{{\mathrm{ON}}}}}{W} = \frac{{I_{{\mathrm{DS}},{\mathrm{SAT}}}}}{W} = C_{{\mathrm{OX}}}v_{{\mathrm{SAT}}}\left( {V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}}} \right) = qn_{\mathrm{S}}v_{{\mathrm{SAT}}}$$
(6)

However, in order to observe current saturation due to velocity saturation, the drain bias must meet the criterion given by Eq. (7).

$$L_{{\mathrm{CH}}}\frac{{v_{{\mathrm{SAT}}}}}{{\mu _{g_{\mathrm{m}}}}} \,<\, V_{{\mathrm{DS}}} \,<\, \left( {V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}} = \frac{{qn_{\mathrm{S}}}}{{C_{{\mathrm{OX}}}}}} \right)$$
(7)

For example, as seen in Fig. 6, current saturation is achieved at VDS = 4 V for 100 nm MoS2 FET and WS2 FET, which is much lower than the corresponding \(V_{{\mathrm{GS}}} - V_{{\mathrm{t}}_{{\mathrm{lin}}}}\) of 11.6 V and 6.7 V, respectively. This explains why the drive current in shorter-channel MoS2 and WS2 FETs display little-to-no channel length dependence for high drain bias (VDS = 5 V), as seen in Fig. 7c, d. Nevertheless, scaled MoS2 and WS2 FETs with channel lengths of 100 nm demonstrate high median drive currents of ION = 54 μA.μm−1 and ION = 17 μA.μm−1, respectively, for VDS = 1 V and ION = 146 μA.μm−1 and ION = 30 μA.μm−1, respectively, for VDS = 5 V. Furthermore, ION at VDS = 5 V can reach as high as 161 μA.μm−1 and 53 μA.μm−1 in “champion” MoS2 and WS2 FETs, respectively. The distribution of ION for VDS = 1 V and VDS = 5 V as a function of LCH is shown in Supplementary Fig. 6 and the corresponding device-to-device variation is summarized in Supplementary Table 7 for MoS2 and WS2 FETs. The higher drive current seen for MoS2 FETs compared to that of WS2 FETs is a direct consequence of lower \(V_{{\mathrm{t}}_{{\mathrm{lin}}}}\), which allows for higher nS in MoS2 channels. Further improvement in the drive current of scaled 2D FETs can be achieved by reducing Rc. Note that, while there are reports of higher ION in large-area grown MoS2 films, none of the earlier studies provide extensive device statistics22,63,64,65. ION for UTB Si MOSFET is 35 nA.μm−1 for 0.9 nm thick Si51. The “champion” devices are benchmarked in Table 3. Supplementary Table 8 shows benchmarking of our statistical study on MoS2 FETs using field-effect mobility and drive current (at VDS = 2 V) with similar channel length dependent statistical studies from the literature. The mean and standard deviation is compared with the LCH dependence and plotted in Supplementary Fig. 7. Better performance is seen for our channel length dependence study compared to ref. 66 for both the drive current and mobility.

Finally, saturation velocity (vSAT) is another key material parameter that determines ION in scaled FETs. This is because at low lateral electric field (ξ) the average electron drift velocity increases linearly through the mobility (\(v_{\mathrm{d}} = \mu _{{\mathrm{FE}}}\xi\)), but at large electric fields, which are easily achievable in sub-micron FETs, the carrier velocity saturates. Thus, ION becomes less dependent on μFE and is instead proportional to vSAT, following Eq. (6). Additionally, high vSAT is needed for faster switching11. Figure 7e–h show the extraction of vSAT and the distribution of vSAT for MoS2 and WS2, respectively. The linear dependence of the saturation current (IDS,SAT) on nS following Eq. (6), is used to extract vSAT. Median vSAT values of 6.4 × 105 cm.s−1 and 4 × 105 cm.s−1 and “champion” vSAT values of 1.1 × 106 cm.s−1 and 6.9 × 105 cm.s−1 are obtained for MoS2 and WS2, respectively. The corresponding device-to-device variations are summarized in Supplementary Table 9. The vSAT values are significantly lower compared to bulk Si with vSAT ≈ 107 cm.s−167,68. Nathawat et al. have reported higher vSAT ≈ 6 × 106 cm.s−1 in CVD grown monolayer MoS269. However, their measurements were done using nanosecond range pulses to reduce the impact of self-heating and hot carrier capture by deep oxide traps. For WS2, this is the first report of vSAT.

Discussion

In conclusion, we have performed a detailed study of device-to-device variation and impact of channel length scaling on the electrical parameters, such as threshold voltage, subthreshold slope, density of interface trap states, ratio of minimum to maximum current, field-effect electron mobility, drive current, contact resistance, and saturation velocity, of MOCVD grown MoS2 and WS2 monolayer based FETs using statistical measures such as median, mean, standard deviation, and minimum/maximum values and have benchmarked our findings against other similar reports from 2D literature as well as UTB Si FETs. While in absolute terms the spatial variations in the respective benchmarking parameters appear to be large for MoS2 and WS2 FETs, when compared at scaled oxide thickness, our results are not significantly different from the projected variations for UTB Si FETs. Our “champion” long-channel MoS2 and WS2 FETs with LCH = 5 μm demonstrated electron mobilities of 30 cm2 V−1 s−1 and 33 cm2 V−1 s−1, respectively, when extracted using peak transconductance and 46 cm2 V−1 s−1 and 33 cm2 V−1 s−1, respectively, when extracted using TLM method. For synthetic monolayer WS2 films, these are the highest reported room temperature electron mobilities, 1.5X better than the best report from the literature. Similarly, our “champion” shortest channel length MoS2 and WS2 FETs, with LCH = 100 nm, demonstrated drive currents as high as 161 μA.μm−1 and 53 μA.μm−1 for VDS = 5 V at carrier densities of nS = 1 × 1013 cm−2 and 4.4 × 1012 cm−2, respectively, in spite of the presence of high contact resistances. We attribute our accomplishments to the epitaxial growth of highly crystalline 2D monolayers on sapphire substrate via MOCVD at 1000 °C using chalcogen and sulfur precursors that minimize carbon contamination in the film, as well as to the clean transfer of the film from the growth substrate to the device fabrication substrate. Our findings suggest that 2D FETs are promising alternatives for future VLSI circuits.

Methods

MOCVD growth

Uniform monolayer deposition was achieved in a cold-wall horizontal reactor with an inductively heated graphite susceptor equipped with wafer rotation as previously described27. Molybdenum hexacarbonyl (Mo(CO)6) and tungsten hexacarbonyl (W(CO)6) were used as metal precursors while hydrogen sulfide (H2S) was the chalcogen source with H2 as the carrier gas. Mo(CO)6 maintained at 10 °C and 950 Torr in a stainless-steel bubbler was used to deliver 0.036 sccm. W(CO)6 maintained in a bubbler at 10 °C and 760 Torr delivered 6.4 × 10−4 sccm. The flow rate of H2S was 400 sccm and the reactor pressure was 50 Torr for both sulfides. MoS2 was deposited in a single step process at 1000 °C where coalesced monolayer growth across the 2″ wafer was achieved in 18 min. WS2 was deposited using a multi-step process with nucleation at 850 °C and lateral growth at 1000 °C, which resulted in coalesced monolayer growth across the 2″ wafer in 10 min28. In both cases, after growth, the substrate was cooled in H2S to 300 °C to inhibit decomposition of the MoS2 and WS2 films.

Material characterization

A Bruker Icon atomic force microscope was used to measure surface morphology and film thickness. Scanasyst AFM tips with a nominal tip radius of ≈2 nm and spring constant of 0.4 Nm−1 were used in the peak-force tapping mode for the measurements. Photoluminescence (PL) maps were acquired over a 5 × 5 μm2 area with a laser wavelength of 532 nm and 300 grooves per mm grating in a WITec apyron Confocal Raman Microscope. A PANalytical MRD diffractometer with a 5-axis cradle was used for in-plane X-ray diffraction characterization of the sulfide films70. A Cu anode X-ray tube operated at 40 kV accelerating voltage and 45 mA filament current was used as the X-ray source. On the primary beam side, a mirror with ¼° slit and Ni filter were used to filter the Cu Kα line. On the diffracted beam side, an 0.27° parallel plate collimator with 0.04 rad Soller slits with PIXcell detector in open detector mode were employed. To determine the in-plane epitaxial relation of the film with respect to a substrate, sample surface was ≈2–4° away from the X-ray incidence plane.

Transfer of monolayer films

Both the MoS2 and WS2 films were grown on 2″ sapphire wafers. The 2″ sapphire wafers were then cut into 1 × 1 cm2 pieces. For each material, two (2) 1 × 1 cm2 sapphire substrates were chosen, one corresponding to the center and another one corresponding to the edge of the 2-inch wafer. To fabricate the FETs, monolayer MoS2 and WS2 films grown on sapphire substrates were transferred onto 1 × 1 cm2 device fabrication substrates, i.e., 50 nm Al2O3 on Pt/TiN/p++-Si, using a PMMA (polymethyl-methacrylate) -assisted wet transfer process. First, the sapphire substrate with the monolayer film was spin coated with PMMA and then baked at 180 °C for 90 s. The corners of the spin coated films were scratched using a razor blade and immersed inside a 1 M NaOH solution kept at 90 °C. Capillary action drew NaOH into the substrate/film interface, separating the PMMA/monolayer film stack from the sapphire substrate. The separated film was then rinsed multiple times inside a water bath and finally transferred onto the 50 nm alumina substrate and baked at 50 °C and 70 °C for 10 min each to remove moisture and residual PMMA, ensuring a pristine interface.

Gate dielectric fabrication

Direct replacement of thermally oxidized SiO2 with a high-κ dielectric such as Al2O3 grown via atomic layer deposition (ALD) is a logical choice to scale the EOT. However, we found that a Al2O3/p++-Si interface is not ideal for back gated FET fabrication owing to higher gate leakage current, more interface trap states, and large hysteresis, all of which negatively impact the performance of the device. Replacing Si with Pt, a large work function metal (5.6 eV) allows for minimal hysteresis and trap state effects71. Since Pt readily forms a Pt silicide at temperatures as low as 300 °C, a 20 nm TiN diffusion barrier deposited by reactive sputtering was placed between the p++ Si and the Pt, permitting subsequent high temperature processing72. This conductive TiN diffusion barrier allows the back-gate voltage to be applied to the substrate, thus simplifying the fabrication and measurement procedures. The polycrystalline Pt introduces very little surface roughness to the final Al2O3 surface, with a rms roughness of 0.7 nm.

Device fabrication

Back gated field-effect transistors (FET) are fabricated using e-beam lithography. To define the channel region the substrate is spin coated with PMMA and baked at 180 °C for 90 s. The photoresist is then exposed to e-beam and developed using 1:1 mixture of 4-methyl-2-pentanone (MIBK) and 2 propanol (IPA). The monolayer MoS2 film is subsequently etched using sulfur hexafluoride (SF6) at 5 °C for 30 s. Next the sample is rinsed in acetone and IPA to remove the photoresist. In order to fabricate the source/drain contacts the substrate is again spin coated with MMA and PMMA followed by the e-beam lithography, developed using MIBK and IPA, and e-beam evaporation of 40 nm Ni/30 nm Au stack. Finally, the photoresist is rinsed away by lift off process using acetone and IPA.

Electrical characterization

Lake Shore CRX-VF probe station and Keysight B1500A parameter analyzer were used to perform the electrical characterization at room temperature in high vacuum (≈10−6 Torr). Standard DC sweeps are used for the measurements of transfer and output characteristics of all devices. To ensure that the FETs are stabilized, they are conditioned by multiple repetitions of the same measurement. The transfer characteristics are measured three times to condition each FET and the fourth measurement is used for the analysis. The output characteristics are measured twice following the transfer characteristics and the second measurement is used for the analysis. We have found that no burn-in procedure is needed to ensure proper contact formation. Both MoS2 and WS2 FETs were measured as-fabricated.

Reporting summary

Further information on research design is available in the Nature Research Reporting Summary linked to this article.