Abstract
This article mainly focuses on the impact on interface trap charges (ITCs) on dual gate source-drain Schottky barrier tunnel field effect transistor (D-G-S-D-STFET) using a high-k dielectric material. Here the high-k material raises the coupling capacitance between the channel and the gate electrode, therefore increases the charge concentration more than a conventional device because of the additional dual-source region. A higher Ion/Ioff current ratio and a reduced off-state leakage are obtained in the design of D-G-S-D-STFET. Moreover, the comparison of the D-G-S-D-STFET device is made with both the dual-metal gate TFET and conventional STFET. Further, the DC and analog/RF performances are characterized by Silvaco TCAD in terms of transfer characteristics (ID–VGS), cut-off frequency (fT), transconductance (gm), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Comparatively to the conventional structures at a gate length of 40 nm has been observed that the Cut-off Frequency (fT) and the TGF are increased in the proposed device to 60 GHz and 259 V−1 range respectively with the positive and negative trap charges. Hence, the results verify that the D-G-S-D-STFET is more suitable for high-frequency applications.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Data availability
The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
References
Ahish S, Sharma D, Nithin Kumar YB, Vasantha MH (2016) Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping. IEEE Trans Electron Devices 63(1):288–295. https://doi.org/10.1109/TED.2015.2503141
Ashok T, Pandey CK (2023) Reduction of corner effect in ZG-ES-TFET for improved electrical performance and its reliability analysis in the presence of traps. ECS J Solid State Sci Technol 12(7):071005. https://doi.org/10.1149/2162-8777/ace656
Dash S, Sahoo GS, Mishra GP (2016) Improved cut-off frequency for cylindrical gate TFET using source delta doping. Procedia Technol 25:450–455. https://doi.org/10.1016/j.protcy.2016.08.131
Datta E, Chattopadhyay A, Mallik A, Omura Y (2020) Temperature dependence of analog performance, linearity, and harmonic distortion for a Ge-source tunnel FET. IEEE Trans Electron Devices 67(3):810–815. https://doi.org/10.1109/TED.2020.2968633
Hur J, Jeong WJ, Shin M, Choi Y-K (2017) Schottky tunneling effects in a tunnel FET. IEEE Trans Electron Devices 64(12):5223–5229. https://doi.org/10.1109/TED.2017.2757260
Kale S (2020) Performance improvement and analysis of PtSi Schottky barrier p-MOSFET based on charge plasma concept for low power applications. SILICON 12(3):479–485. https://doi.org/10.1007/s12633-019-00161-1
Kale S (2023) Investigation of dual metal gate Schottky barrier MOSFET for suppression of ambipolar current. IETE J Res 69(1):404–409. https://doi.org/10.1080/03772063.2020.1823250
Kale S, Chandu MS (2022) Dual metal gate dielectric engineered dopant segregated Schottky barrier MOSFET with reduction in ambipolar current. SILICON 14(3):935–941. https://doi.org/10.1007/s12633-020-00921-4
Karthik KRN, Pandey CK (2024) GaSb/GaAs Type-II heterojunction GAA-TFET with core source for enhanced analog/RF performance and reliability. Int J Numer Model 37(2):e3167. https://doi.org/10.1002/jnm.3167
Kaushal P, Khanna G (2022) MoS2 based thickness engineered tunnel field-effect transistors for RF/analog applications. Mater Sci Semicond Process 151:107016. https://doi.org/10.1016/j.mssp.2022.107016
Kumar P (2022) Performance analysis of double gate dielectric modulation in Schottky FET As biomolecule sensor. SILICON 14:4767–4773
Kumar P, Bhowmick B (2017a) 2-D analytical modeling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET. J Comput Electron 16(3):658–665. https://doi.org/10.1007/s10825-017-1011-x
Kumar P, Bhowmick B (2017b) 2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET. Superlatt Microstruct 109:805–814. https://doi.org/10.1016/j.spmi.2017.06.001
Kumar P, Bhowmick B (2018) A physics-based threshold voltage model for hetero-dielectric dual material gate Schottky barrier MOSFET. Int J Numer Model 31(5):e2320. https://doi.org/10.1002/jnm.2320
Kumar P, Bhowmick B (2020) Source-drain junction engineering Schottky barrier MOSFETs and their mixed mode application. SILICON 12(4):821–830. https://doi.org/10.1007/s12633-019-00170-0
Kumar P, Arif W, Bhowmick B (2018) Scaling of dopant segregation Schottky barrier using metal strip buried oxide MOSFET and its comparison with conventional device. SILICON 10(3):811–820. https://doi.org/10.1007/s12633-016-9534-5
Kumar P, Esakki P, Agarwal L, PeddaKrishna SK, Bhowmick B (2022a) Recent progress on sensitivity analysis of Schottky field effect transistor based biosensors. SILICON. https://doi.org/10.1007/s12633-022-01994-z
Kumar P, Vinod A, Dharavath K, Bhowmick B (2022a) Analysis and simulation of Schottky tunneling using Schottky barrier FET with 2-D analytical modeling. SILICON 14(3):831–837. https://doi.org/10.1007/s12633-020-00879-3
Kwatra P, Singh SV, Nigam K (2023a) Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor. Microelectron Reliab 140:114872. https://doi.org/10.1016/j.microrel.2022.114872
Kwatra P, Nigam K, Singh SV (2023b) Design and performance evaluation of a novel dual tunneling based TFET considering trap charges for reliability improvement. Silicon 15:2407–2425
Lee JW, Choi WY (2020) Design guideline of tunnel field-effect transistors (TFETs) considering negative differential transconductance (NDT). Solid-State Electron 163:107659. https://doi.org/10.1016/j.sse.2019.107659
Madan J, Chaujar R (2016) Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans Device Mater Relib 16(2):227–234. https://doi.org/10.1109/TDMR.2016.2564448
Mohankumar N, Syamal B, Sarkar CK (2010) Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. IEEE Trans Electron Devices 57(4):820–826. https://doi.org/10.1109/TED.2010.2040662
Nigam K, Kondekar P, Sharma D (2016) DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor. Superlatt Microstruct 92:224–231. https://doi.org/10.1016/j.spmi.2016.01.032
Pandey CK, Singh A, Chaudhury S (2021) A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET. Microelectron Reliab 122:114166. https://doi.org/10.1016/j.microrel.2021.114166
Pratap Y, Haldar S, Gupta RS, Gupta M (2014) Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design. IEEE Trans Device Mater Reliab 14(1):418–425. https://doi.org/10.1109/TDMR.2013.2296524
Qiu Y, Wang R, Huang Q, Huang Ru (2014) A comparative study on the impacts of interface traps on tunneling FET and MOSFET. IEEE Trans Electron Devices 61(5):1284–1291. https://doi.org/10.1109/TED.2014.2312330
Raad BR, Sharma D, Kondekar P, Nigam K, Yadav DS (2016) Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and rf performance improvement: a proposal, design, and investigation. IEEE Trans Electron Devices 63(10):3950–3957. https://doi.org/10.1109/TED.2016.2600621
Sarkar A, Sarkar CK (2013) RF and analogue performance investigation of DG tunnel FET. Int J Electron Lett 1(4):210–217. https://doi.org/10.1080/21681724.2013.854158
Singh P, Yadav DS (2022) Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET. Curr Appl Phys 44:90–101. https://doi.org/10.1016/j.cap.2022.09.014
Singh PK et al (2019) Impact of gate dielectrics on analog/RF performance of double gate tunnel field effect transistor. In: 2019 3rd International conference on electronics, materials engineering and nano-technology (IEMENTech), Kolkata, India, Aug. 2019, pp 1–5. https://doi.org/10.1109/IEMENTech48150.2019.8981283
Singh KS, Kumar S, Nigam K (2020a) Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Trans Device Mater Reliab 20(2):404–412. https://doi.org/10.1109/TDMR.2020.2984669
Singh PK et al (2020b) Influence of temperature on analog/radio frequency appearances of heterojunction cylindrical gate tunnel FETs. In: 2020 IEEE international conference on computing, power and communication technologies (GUCON), Greater Noida, India, Oct. 2020, pp 511–515. https://doi.org/10.1109/GUCON48875.2020.9231207
Singh AK, Tripathy MR, Baral K, Singh PK, Jit S (2020c) Design and investigation of lateral HfO2/SiO2 gate stacked TFET on SELBOX substrate for low power and high-frequency applications. In: 2020 URSI regional conference on radio science (URSI-RCRS), Varanasi, India, Feb. 2020, pp 1–4. https://doi.org/10.23919/URSIRCRS49211.2020.9113584
Tiwari S, Saha R (2022) DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: a simulation study. Microelectron Reliab 137:114780. https://doi.org/10.1016/j.microrel.2022.114780
Tripathy MR, Singh AK, Samad A, Singh PK, Baral K, Jit S (2020) Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET. Semicond Sci Technol 35(10):105014. https://doi.org/10.1088/1361-6641/aba418
Vinod A, Kumar P, Bhowmick B (2019) Impact of ferroelectric on the electrical characteristics of silicon–germanium-based heterojunction Schottky barrier FET. AEU-Int J Electron C 107:257–263. https://doi.org/10.1016/j.aeue.2019.05.030
Wen J, Chaganti VRSK, Truttmann TK, Liu F, Jalan B, Koester SJ (2021) SrSnO3 metal-semiconductor field-effect transistor With GHz operation. IEEE Electron Device Lett 42(1):74–77. https://doi.org/10.1109/LED.2020.3040417
Author information
Authors and Affiliations
Contributions
All authors reviewed the manuscript.
Corresponding author
Ethics declarations
Conflict of interest
The authors declare no competing interests.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Anusuya, P., Kumar, P. Analysis of interface trap charges on RF/analog performances of dual-gate-source-drain Schottky FET for high-frequency applications. Multiscale and Multidiscip. Model. Exp. and Des. (2024). https://doi.org/10.1007/s41939-024-00419-1
Received:
Accepted:
Published:
DOI: https://doi.org/10.1007/s41939-024-00419-1