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Performance enhancement of junctionless silicon nanotube gate-all-around FETs for nano-scaled devices

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Abstract

This paper presents a novel structure of TSV-based silicon nanotube gate-all-around FETs (both junction-based and junctionless) along with their electrical characteristics using Silvaco ATLAS 3D device simulator. In comparison, the junctionless silicon nanotube gate-all-around structures presented an excellent performance improvement over the junction-based structures in terms of short channel effects, an improved drain-induced barrier lowering of ~ 28% for n-MOS and ~ 22% for p-MOS, and improved (ION/IOFF) switching ratio of ~ 68% for n-MOS and ~ 42% for p-MOS. Similarly, the junctionless structure shows a steep subthreshold value very close to the ideal value (~ 60 mv/dec). Furthermore, the static and transient characteristics of CMOS inverter circuits designed using the complementary device architecture have been explored using mixed-mode simulations. The noise margin and propagation delay of the circuit are analyzed and are found to agree with the information available in the literature for nano-scaled devices.

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Authors and Affiliations

  1. Centre for Development of Advanced Computing, Mohali, India

    Balwinder Singh

  2. Chandigarh University, Mohali, India

    Rekha Devi

  3. Chandigarh College of Engineering -CGC Landran, Mohali, India

    Shashi Bala

Authors
  1. Balwinder Singh
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  2. Rekha Devi
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  3. Shashi Bala
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Contributions

BS wrote the paper and also guided the other two authors in simulation work. RD did the reviews and figure preparations. etc. SB simulated the results and compared the work with existing work

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Correspondence to Balwinder Singh.

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Singh, B., Devi, R. & Bala, S. Performance enhancement of junctionless silicon nanotube gate-all-around FETs for nano-scaled devices. Multiscale and Multidiscip. Model. Exp. and Des. (2024). https://doi.org/10.1007/s41939-024-00402-w

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