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Design and implementation of high speed, low complexity FFT/IFFT processor using modified mixed radix-24–22-23 algorithm for high data rate applications

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Abstract

A modified mixed radix algorithm with low complexity based Fast Fourier Transform (FFT) processor for large data rate applications is presented in this paper. In order to reduce the complexity of twiddle factor multiplication an improved FFT/IFFT architecture has been derived. A novel Modified Mixed Radix-24-22-23 (MMR-24-22-23) algorithm is derived and implemented in this work with a 90 nm CMOS processing technology operating at 1.2 V. From the simulation results, the proposed algorithm reduces the power consumption and area when compared with the existing models. The power consumption of the proposed design is approximately 90.4 mW, which reduces the power consumption by 22.7%. Also, the normalized area of the complex constant multiplier is 14.88, which reduces the area by 26.19% when compared with existing architectures. A canonical signed digit constant multiplier with a common sub-expression sharing method is incorporated to further reduce the complexity of the multiplier by a factor of over 33%.

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Authors and Affiliations

  1. Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science and Technology, Chennai, India

    C. A. Arun

  2. Pavai College of Technology, Namakkal, India

    M. Sahayasheela

  3. R & D Embedded Engineer, Connected Digital Systems Private Limited, Chennai, India

    G. Gnanaguru

Authors
  1. C. A. Arun
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  2. M. Sahayasheela
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  3. G. Gnanaguru
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Arun, C.A., Sahayasheela, M. & Gnanaguru, G. Design and implementation of high speed, low complexity FFT/IFFT processor using modified mixed radix-24–22-23 algorithm for high data rate applications. Int. j. inf. tecnol. 15, 161–168 (2023). https://doi.org/10.1007/s41870-022-01128-z

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