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A Novel Physical Unclonable Function Based on Hybrid Current Mirror

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Abstract

Intrinsic manufacturing process variations are extensive, unpredictable, and inevitable in modern semiconductor technology. This is advantageously utilized in physically unclonable function (PUF) circuits for enhancing hardware and software security. Among widely-known PUF variants, the Arbiter PUF based on digital building blocks has a regular structure and low hardware footprint; however, it is susceptible to machine learning-based modeling attacks. In this work, we propose a new low-power and reliable PUF, based on the hybrid current mirror inverter (CMI). The proposed PUF circuit exploits the process variation-induced randomness in the CMI circuits to generate instance-specific challenge-response characteristics. The current mirror ensures the stability of the overdrive voltages across all the transistors in the CMI blocks, thereby improving the reliability of the proposed PUF. The PUF circuit was simulated at a 45 nm CMOS technology node, and its major performance metrics were evaluated. The simulation results demonstrated that the proposed PUF has excellent performance metrics while having low hardware and resource footprint. In addition, the proposed PUF demonstrated robustness against machine learning-based model-building attacks.

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References

  1. Tanaka Y, Bian S, Hiromoto M, Sato T (2018) Coin flipping PUF: a novel PUF with improved resistance against machine learning attacks. IEEE Trans Circuits Syst II Express Briefs 65(5):602–606

    Google Scholar 

  2. Zhang F, Yang S, Plusquellic J, Bhunia S (2016) Current based PUF exploiting random variations in SRAM cells. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 277–280. IEEE

  3. Kumar R, Patil VC, Kundu S (2011) Design of unique and reliable physically unclonable functions based on current starved inverter chain. In: 2011 IEEE Computer Society Annual Symposium on VLSI, pp 224–229. IEEE

  4. Maiti A, Gunreddy V, Schaumont P (2013) A systematic method to evaluate and compare the performance of physical unclonable functions. Springer

  5. Mathew J, Chakraborty RS, Sahoo DP, Yang Y, Pradhan DK (2015) A novel memristor-based hardware security primitive. ACM Trans Embed Comput Syst 14(3). https://doi.org/10.1145/2736285

  6. Helfmeier C, Boit C, Nedospasov D, Seifert J-P (2013) Cloning physically unclonable functions, pp 1–6. https://doi.org/10.1109/HST.2013.6581556

  7. Santikellur P, Bhattacharyay A, Chakraborty RS (2019) Deep learning based model building attacks on arbiter PUF compositions. IACR Cryptol. ePrint Arch. 2019:566

    Google Scholar 

  8. Khalafalla M, Gebotys C (2019) PUFs deep attacks: enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFs. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 204–209. IEEE

  9. Hospodar G, Maes R, Verbauwhede I (2012) Machine learning attacks on 65nm Arbiter PUFs: accurate modeling poses strict bounds on usability. In: 2012 IEEE International Workshop on Information Forensics and Security (WIFS), pp 37–42. IEEE

  10. Ikezaki Y, Nozaki Y, Yoshikawa M (2016) Deep learning attack for physical unclonable function. In: 2016 IEEE 5th Global Conference on Consumer Electronics, pp 1–2. IEEE

  11. Santikellur P, Chakraborty RS (2021) A computationally efficient tensor regression network-based modeling attack on XOR Arbiter PUF and its variants. IEEE Trans Comput Aided Des Integr Circuits Syst 40(6):1197–1206. https://doi.org/10.1109/TCAD.2020.3032624

    Article  Google Scholar 

  12. Rührmair U, Sehnke F, Sölter J, Dror G, Devadas S, Schmidhuber J (2010) Modeling attacks on physical unclonable functions. In: Proceedings of the 17th ACM Conference on Computer and Communications Security, pp 237–249

  13. Rührmair U, Sölter J, Sehnke F, Xu X, Mahmoud A, Stoyanova V, Dror G, Schmidhuber J, Burleson W, Devadas S (2013) PUF modeling attacks on simulated and silicon data. IEEE Trans Inf Forensics Secur 8(11):1876–1891

    Article  Google Scholar 

  14. Gassend B, Clarke D, VanDijk M, Devadas S (2002) Silicon physical random functions. In: Proceedings of the 9th ACM Conference on Computer and Communications Security, pp 148–160

  15. Becker GT (2015) The gap between promise and reality: on the insecurity of XOR arbiter PUFs. In: Cryptographic Hardware and Embedded Systems–CHES 2015: 17th International Workshop, Saint-Malo, France, September 13-16, 2015, Proceedings 17, pp 535–555. Springer

  16. Kumar R, Burleson W (2014) On design of a highly secure PUF based on non-linear current mirrors. In: 2014 IEEE International Symposium on Hardware-oriented Security and Trust (HOST), pp 38–43. IEEE

  17. Vijayakumar A, Kundu S (2015) A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. In: 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 653–658. IEEE

  18. Guo Q, Ye J, Gong Y, Hu Y, Li X (2016) Efficient attack on non-linear current mirror PUF with genetic algorithm. In: 2016 IEEE 25th Asian Test Symposium (ATS), pp. 49–54. IEEE

  19. Wang Z, Chen Y, Patil A, Chang C-H, Basu A (2017) Current mirror array: a novel lightweight strong PUF topology with enhanced reliability. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1–4. IEEE

  20. Wang Z, Chen Y, Patil A, Jayabalan J, Zhang X, Chang C-H, Basu A (2017) Current mirror array: a novel circuit topology for combining physical unclonable function and machine learning. IEEE Trans Circuits Syst I Regul Pap 65(4):1314–1326

    Article  Google Scholar 

  21. Shah N, Chatterjee D, Sapui B, Mukhopadhyay D, Basu A (2021) Introducing recurrence in strong PUFs for enhanced machine learning attack resistance. IEEE J Emerg Sel Topics Circ Syst 11(2):319–332. https://doi.org/10.1109/JETCAS.2021.3075767

    Article  Google Scholar 

  22. Paul SD, Bhunia S (2022) CurIAs: current-based IC authentication by exploiting supply current variations. IEEE Trans Comput

  23. Zhao X, Gan P, Zhao Q, Liang D, Cao Y, Pan X, Bermak A (2019) A 124 fJ/bit cascode current mirror array based PUF with 1.50% native unstable bit ratio. IEEE Trans Circuits Syst I Regul Paper 66(9):3494–3503

  24. Qin Z, Shintani M, Kuribara K, Ogasahara Y, Sato T (2020) Organic current mirror PUF for improved stability against device aging. IEEE Sens J 20(14):7569–7578

    Article  ADS  CAS  Google Scholar 

  25. Berkeley U (2022) Berkeley Predictive Technology Model (PTM) model for CMOS: V4.0.[Online]. Available: http://ptm.asu.edu/

  26. Qian K (2015) Variability modeling and statistical parameter extraction for cmos devices. PhD thesis, UC Berkeley

  27. Razavi B (2002) Design of analog CMOS integrated circuits. McGraw-Hill Education

  28. Azcona C, Calvo B, Celma S, Medrano N, Sanz MT (2014) Precision CMOS current reference with process and temperature compensation. In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp 910–913. IEEE

  29. Chakraborty AS, Mondal SA, Rahaman H (2016) Low noise and low power switched biased CSA with clocked reset and minimal PVT variation for APD based positron emission tomography. Analog Integr Circ Sig Process 88:495–504

    Article  Google Scholar 

  30. Fischer V (2012) A closer look at security in random number generators design. In: International Workshop on Constructive Side-channel Analysis and Secure Design, pp 167–182. Springer

  31. Della Sala R, Bellizia D, Scotti G (2021) A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators. IEEE Trans Circuits Syst II Express Briefs 69(3):1672–1676

    Google Scholar 

  32. Chen T, Ma Y, Lin J, Cao Y, Lv N, Jing J (2021) A lightweight full entropy TRNG with on-chip entropy assurance. IEEE Trans Comput Aided Des Integr Circuits Syst 40(12):2431–2444

    Article  Google Scholar 

  33. Gao B, Lin B, Li X, Tang J, Qian H, Wu H (2022) A unified PUF and TRNG design based on 40-nm RRAM with high entropy and robustness for IoT security. IEEE Trans Electron Devices 69(2):536–542

    Article  ADS  CAS  Google Scholar 

  34. Danesh M, Venkatasubramaniyan AB, Kapoor G, Ramesh N, Sadasivuni S, Chandrasekaran ST, Sanyal A (2020) Unified analog PUF and TRNG based on current-steering DAC and VCO. IEEE Trans Very Large Scale Integr (VLSI) Syst 28(11):2280–2289

  35. Pedregosa F, Varoquaux G, Gramfort A, Michel V, Thirion B, Grisel O, Blondel M, Prettenhofer P, Weiss R, Dubourg V, Vanderplas J, Passos A, Cournapeau D, Brucher M, Perrot M, Duchesnay E (2011) Scikit-learn: machine learning in Python. J Mach Learn Res 12:2825–2830

    MathSciNet  Google Scholar 

  36. Google (2022) Google Colaboratory Accessed: Jan. 10, 2022. [Online]. Available: https://colab.research.google.com

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Acknowledgements

We also would like to acknowledge http://ptm.asu.edu/ for sharing the 45 nm Predictive Technology Model (PTM) model for CMOS: V4.0.

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Authors and Affiliations

  1. Department of Electronics, Cochin University of Science and Technology, Kochi, Kerala, India

    Gisha C. G.

  2. Berkeley Wireless Research Center, UC Berkeley, Berkeley, CA, USA

    Ananda Sankar Chakraborty

  3. Department of Computer Science and Engineering, IIT Kharagpur, Kharagpur, West Bengal, India

    Rajat Subhra Chakraborty

  4. Department of Computer Science, Cochin University of Science and Technology, Kochi, India

    Bijoy Antony Jose

  5. Department of Computer Science, IIT Patna, Patna, Bihar, India

    Jimson Mathew

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  1. Gisha C. G.
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  2. Ananda Sankar Chakraborty
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  5. Jimson Mathew
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Corresponding author

Correspondence to Bijoy Antony Jose.

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Funding

This work is supported by the DST-SERB-ICPS project titled “Energy Efficient Cyber Security Implementation for Internet of Things” (Grant ID:DST/ICPS/CPS-Individual/2018/392 (C)), with Dr. Bijoy as Principal Investigator and Dr. Jimson Mathew as Co-Principal Investigator. Gisha C. G. is grateful for the research fellowship from Kerala State Council for Science, Technology and Environment (KSCSTE).

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Competing Interests

The authors declare no competing interests.

Author Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by Gisha C. G. The first draft of the manuscript was written by Gisha C. G and all authors commented on previous versions of the manuscript. All authors read and reviewed the manuscript.

Data Availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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C. G., G., Chakraborty, A., Chakraborty, R. et al. A Novel Physical Unclonable Function Based on Hybrid Current Mirror. J Hardw Syst Secur 7, 125–137 (2023). https://doi.org/10.1007/s41635-023-00138-y

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  • DOI: https://doi.org/10.1007/s41635-023-00138-y

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