Skip to main content
Log in

Securing 3rd-Party HDL IP: a Feasibility Study Using Evolutionary Methods

  • Published:
Journal of Hardware and Systems Security Aims and scope Submit manuscript

Abstract

The increasing globalization of the intellectual property (IP) industry has added a new risk for designers when using 3rd-party programs. Malicious entities have more opportunities to insert Hardware Trojans (HT) into these 3rd-party IPs, which can often remain undetected by conventional testing procedures. Even in a case where these Trojans could be detected from a full testing suite, the time associated with running the full suite could be infeasible, or the full testing suite might not be available to the designer. This work performs a feasibility study on the use of evolutionary computing (EC) to evolve 3rd-party hardware design language (HDL) IPs to remove HT from an infected IP. We measure the strength and weaknesses of EC by testing different mutations schemes across various evolutionary goals, with the use of full and partial testing suites. The scalability of the approach is then shown in higher dimensions, while showing that the synthesized designs of the evolved programs have no additional overhead compared to the original uninfected code when tested in Vivado. We then conclude with some suggestions of future works in the area of targeted evolution on larger circuits containing more complex Hardware Trojans.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

Code Availability

The code for this work is available under the MIT license at https://github.com/king2b3/GP.

References

  1. Mal-Sarkar S, Krishna A, Ghosh A, Bhunia S (2014) Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures. In Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, pp 287–292

  2. Tehranipoor M, Koushanfar F (2016) A survey of hardware trojan taxonomy and detection. IEEE Design & Test of Computers 01:1–1

    Google Scholar 

  3. Jin Y, Kupp N, Makris Y (2009) Experiences in hardware Trojan design and implementation. In 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, IEEE, pp 50–57

  4. Wei S, Potkonjak M (2013) The undetectable and unprovable hardware trojan horse. In 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), IEEE, pp 1–2

  5. Agrawal D, Baktir S, Karakoyunlu D, Rohatgi P, Sunar B (2007) Trojan detection using IC fingerprinting. In 2007 IEEE Symposium on Security and Privacy (SP’07), IEEE, pp 296–310

  6. Alkabani Y, Koushanfar F (2007) Active hardware metering for intellectual property protection and security. In USENIX security symposium, pp 291–306

  7. Liu H, Luo H, Wang L (2011) Design of hardware trojan horse based on counter. In 2011 International Conference on Quality, Reliability, Risk, Maintenance, and Safety Engineering, IEEE, pp 1007–1009

  8. Kashtan N, Alon U (2005) Spontaneous evolution of modularity and network motifs. Proceedings of the National Academy of Sciences 102(39):13773–13778

    Article  Google Scholar 

  9. Koza JR, Andre D, Keane MA, Bennett FH III (1999) Genetic programming III: Darwinian invention and problem solving, vol 3. Morgan Kaufmann

    MATH  Google Scholar 

  10. Larchev GV, Lohn J (2006) D. Evolutionary based techniques for fault tolerant field programmable gate arrays. In 2nd IEEE International Conference on Space Mission Challenges for Information Technology (SMC-IT’06), IEEE, pp 8–pp

  11. Ping L, Yu S (2010) An adaptive binary particle swarm optimization for evolvable hardware. In 2010 2nd International Conference on Industrial and Information Systems, vol. 1, IEEE, pp 98–101

  12. Collins Z (2019) Hardware trojans in FPGA device IP: solutions through evolutionary computation. PhD thesis, University of Cincinnati

  13. Collins Z, King B, Jha R, Kapp D, Ralescu A (2019) Evolvable hardware for security through diverse variants. In 2019 IEEE National Aerospace and Electronics Conference (NAECON), IEEE, pp 257–261

  14. Chen Z, Guo S, Wang J, Li Y, Lu Z (2019) Toward FPGA security in IoT: a new detection technique for hardware trojans. IEEE Internet of Things Journal 6(4):7061–7068

    Article  Google Scholar 

  15. Cruz J, Farahmandi F, Ahmed A, Mishra P (2018) Hardware Trojan detection using ATPG and model checking. In 2018 31st international conference on VLSI design and 2018 17th international conference on embedded systems (VLSID), IEEE, pp 91–96

  16. Shakya B, He T, Salmani H, Forte D, Bhunia S, Tehranipoor M (2017) Benchmarking of hardware trojans and maliciously affected circuits. Journal of Hardware and Systems Security 1(1):85–102

    Article  Google Scholar 

  17. Yu S, Gu C, Liu W, O’Neill M (2020) A novel feature extraction strategy for hardware trojan detection. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp 1–5

  18. Cohoon J, Kairo J, Lienig J (2003) Evolutionary algorithms for the physical design of VLSI circuits. Springer, Berlin Heidelberg, pp 683–711

    Google Scholar 

  19. Levi D (2000) HereBoy: a fast evolutionary algorithm. In Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware, IEEE, pp 17–24

  20. Gordon GT, Bentley JP (2002) On evolvable hardware. In Soft computing in industrial electronics. Springer, pp 279–323

  21. Popp RL, Montana DJ, Gassner RR, Vidaver G, Iyer S (1998) Automated hardware design using genetic programming, VHDL, and FPGAs. In SMC’98 Conference Proceedings. 1998 IEEE International Conference on Systems, Man, and Cybernetics (Cat. No. 98CH36218), vol. 3, IEEE, pp 2184–2189

  22. Keim M, Drechsler N, Becker B (1999) Combining gas and symbolic methods for high quality tests of sequential circuits. In Proceedings of the ASP-DAC ’99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), vol. 1, pp 315–318

  23. Rudnick E, Patel J, Greenstein G, Niermann T (1997) A genetic algorithm framework for test generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16(9):1034–1044

    Article  Google Scholar 

  24. Rudnick EM, Patel JH, Greenstein GS, Niermann TM (1997) A genetic algorithm framework for test generation. IEEE Transactions on computer-aided design of integrated circuits and systems 16(9):1034–1044

    Article  Google Scholar 

  25. Saha S, Chakraborty RS, Nuthakki SS, Mukhopadhyay D et al (2015) Improved test pattern generation for hardware trojan detection using genetic algorithm and Boolean satisfiability. In International Workshop on Cryptographic Hardware and Embedded Systems, Springer, pp 577–596

  26. Yu X, Fin A, Fummi F, Rudnick E (2002) A genetic testing framework for digital integrated circuits. In 14th IEEE International Conference on Tools with Artificial Intelligence, 2002. (ICTAI 2002). Proceedings, pp 521–526

  27. Eiben AE, Smith JE et al (2003) Introduction to evolutionary computing, vol 53. Springer

    Book  Google Scholar 

  28. Koza JR (1992) Genetic programming: on the programming of computers by means of natural selection, vol. 1. MIT press

  29. Beyer H-G, Schwefel H-P (2002) Evolution strategies-a comprehensive introduction. Natural computing 1(1):3–52

    Article  MathSciNet  Google Scholar 

  30. Xu H (2015) An algorithm for comparing similarity between two trees. arXiv preprint. arXiv: 1508.03381

  31. Zhang K, Shasha D (1989) Simple fast algorithms for the editing distance between trees and related problems. SIAM journal on computing 18(6):1245–1262

    Article  MathSciNet  Google Scholar 

  32. Zhang K, Statman R, Shasha D (1992) On the editing distance between unordered labeled trees. Information processing letters 42(3):133–139

    Article  MathSciNet  Google Scholar 

  33. Banga M, Hsiao MS (2008) A region based approach for the identification of hardware trojans. In 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, IEEE, pp 40–47

  34. Salmani H, Tehranipoor M, Karri R (2013) On design vulnerability analysis and trust benchmarks development. In 2013 IEEE 31st international conference on computer design (ICCD), IEEE, pp 471–474

Download references

Acknowledgements

The authors would like to thank Tyler Westland, Jenna King, Joshua Mayersky, Wayne Stegner, and Siddharth Barve for their help and feedback over the process of this work.

Funding

This research was funded by Defense Associated Graduate Student Innovators project number RY20-9. This material is based on research sponsored by the Air Force Research Laboratory and the Southwestern Council for Higher Education under Agreement FA8650-18-C-1191 P00005, and is PA approved along case number AFRL-2021-1299. The US Government is authorized to reproduce and distribute reprints for governmental purposes notwithstanding any copyright notation thereon.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Bayley King.

Ethics declarations

Conflict of Interest

The authors declare no competing interests.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

King, B., Jha, R., Kebede, T. et al. Securing 3rd-Party HDL IP: a Feasibility Study Using Evolutionary Methods. J Hardw Syst Secur 6, 17–31 (2022). https://doi.org/10.1007/s41635-022-00125-9

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s41635-022-00125-9

Keywords

Navigation