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Power Efficient CNTFET-Based Ternary Comparators

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Abstract

Ternary logic offers faster response and low power consumption for digital systems, which minimizes the connection complexity, chip size and power consumption. Multi-threshold and geometry dependent properties of CNTFET make it a suitable alternative over the traditional Si-MOSFET for ternary logic circuit implementation. The proposed work minimizes the power dissipation, improves the speed and noise margin for designing efficient ternary circuits. In this article, one ternary decoder and two ternary comparators are designed and analysed. The proposed circuits are simulated and compared with existing circuits using HSPICE Synopsys tool. The proposed ternary decoder shows improvement up to 48% and 74% in power dissipation and power delay product, respectively, as compared to existing circuits. The proposed ternary comparator saves 82% power over other ternary comparators. Noise margin for proposed ternary decoder and ternary comparators is increased to up to 21% and 34%, respectively.

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  1. Manipal University - Jaipur Campus, Jaipur, India

    Katyayani Chauhan & Deepika Bansal

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  1. Katyayani Chauhan
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  2. Deepika Bansal
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Correspondence to Deepika Bansal.

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Chauhan, K., Bansal, D. Power Efficient CNTFET-Based Ternary Comparators. J. Inst. Eng. India Ser. B 105, 323–334 (2024). https://doi.org/10.1007/s40031-023-00972-2

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