Abstract
In a communication receiver, an efficient narrow-band filter plays a significant role that can decimate the incoming signals with proper filtering operation. The cascade integrator comb (CIC) works as a high-speed decimation filter for the anti-aliasing process. This paper focuses on a reconfigurable CIC decimator with pruning characteristics that reduce the hardware resources. Also, applying the partitioning method in the decimator factor can reduce the computation time significantly. The modified CIC decimators are simulated using Xilinx ISE 14.7 and then, synthesized the bit streams have been downloaded on Virtex-5 FPGA board to target the XC5VLX50T device. The performance has been analyzed concerning the number of stages and the decimation factors. The proposed three-stage CIC decimator saves the slice registers and power up to 39.84% and 16.17% respectively, as compared to similar types of architectures.
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Acknowledgements
The authors are expressed their sincere gratitude to Maulana Abul Kalam Azad University of Technology, West Bengal for providing the valuable Xilinx tools and FPGA board.
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