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Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAs

  • Research Article-Computer Engineering and Computer Science
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Abstract

Placement of heterogeneous FPGAs has been a complex problem for large designs. In addition, the extensive use of FPGAs in many applications, they have become very popular since last two decades. Hence, robust but simple steps algorithms are must needed for solving different layout problems for heterogeneous FPGAs. Like other design problems, the placement problem of heterogeneous FPGAs has become very hard with the increasing number of the various components and their inter connections. In addition to that routability-aware placement is a must needed solution, since placement without routability awareness may lead to failure of routing. In this paper, a Boolean satisfiability (SAT)-based packing and legalization free placement algorithm called SatPhF has been introduced for Xilinx UltraScale FPGA architectures. The proposed technique reduces the effort given for packing and legalization in the state-of-the-art placement algorithms. Additionally, the proposed approach takes care of congestion to produce an optimized routability-aware placement solutions in terms of wirelength and congestion. This technique performs a novel placement row selection method for a set of cells connected by a net using 2-SAT formulation which is able to optimize wirelength without use of any expensive analytical optimization framework. A new legalized location finding SAT approach has been introduced to find suitable locations for different cells without performing separate legalization step like other state-of-the-art placement algorithms. Finally, a SAT-based placement refinement procedure is introduced to reduce the congestion and making the placement routable. The proposed technique claims that most of the SAT instances created to formulate the placement problem is 2-SAT. The experimental results obtained by the presented approach show its ability to perform placement reasonably well in terms of wirelength and congestion. The results have been compared with four state-of-the-art techniques and show that SatPhF achieves a reasonably well reduction in total wirelength.

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Authors and Affiliations

  1. Department of CSE, National Institute of Technology Silchar, Assam, India

    Shyamapada Mukherjee & Sharbani Purkayastha

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  1. Shyamapada Mukherjee
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  2. Sharbani Purkayastha
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Correspondence to Shyamapada Mukherjee.

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Mukherjee, S., Purkayastha, S. Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAs. Arab J Sci Eng 47, 2255–2270 (2022). https://doi.org/10.1007/s13369-021-06176-4

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  • DOI: https://doi.org/10.1007/s13369-021-06176-4

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