Skip to main content
SpringerLink
Log in

NMR configurations with novel majority voter circuits to mask multiple module faults

  • Original Research
  • Published:
Journal of Ambient Intelligence and Humanized Computing Aims and scope Submit manuscript

Abstract

Mission, safety, and business-critical applications need uninterrupted operation with correct results. But due to the technology shrinking, the microelectronic circuits can be affected by many faults like permanent, transient, and intermittent. So, there is a considerable demand for designing fault-tolerant systems. Hardware redundancy configurations have been widely used to protect or mask faults. In this research article, to mask multiple faults, N-modular redundancy (NMR) configurations are deployed, namely 5-MR and 7-MR configurations, which are implemented to mask two and three function module errors. Two majority voter (MV) circuits with 5-MR and 7-MR have been proposed, respectively. Simulation results are obtained with Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). With ASIC, 120 nm technology is used with BSIM4 Spice simulation parameters. Also, the majority voters are evaluated with a band-pass filter as the function module on Altera DE2-115 FPGA using the Quartus II synthesis tool. The very high-speed integrated circuits hardware description language is used with FPGA implementation. Simulation results reveal that the proposed MV circuits obtain better results than the existing methods.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  • Abdulhay E, Elamaran V, Arunkumar N, Venkataraman V (2018) Fault-tolerant medical imaging system with quintuple modular redundancy (QMR) configurations. J Ambient Intell Humaniz Comput 10:1–13. https://doi.org/10.1007/s12652-018-0748-9

    Article  Google Scholar 

  • Almukhaizim S, Sinanoglu O (2011) Novel hazard-free majority voter for N-modular redundancy-based fault tolerance in asynchronous circuits. IET Comput Digital Tech 5(4):306–315

    Article  Google Scholar 

  • Altera (2013) White paper: introduction to single-event upsets, https://www.altera.com/en_US/pdfs/literature/wp/wp-01206-introduction-single-event-upsets.pdf

  • Argyrides CA, Reviriego P, Pradhan DK, Maestro JA (2010) Matrix-based codes for adjacent error correction. IEEE Trans Nucl Sci 57(4):2106–2111

    Article  Google Scholar 

  • Balasubramanian P (2016) ASIC-based design of NMR system health monitor for mission/safety–critical applications. SpringerPlus 5:1–16

    Article  Google Scholar 

  • Balasubramanian P, Maskell DL (2015) A distributed minority and majority voting based redundancy scheme. Microelectron Reliab 55(9–10):1373–1378

    Article  Google Scholar 

  • Balasubramanian P, Prasad K, Mastorakis NE (2016) A fault tolerance improved majority voter for TMR system architectures. WSEAS Trans Circuits Syst 15:108–122

    Google Scholar 

  • Balasubramanian P, Maskell D, Mastorakis N (2018) Majority and minority voted redundancy scheme for safety-critical applications with error/no-error signaling logic. Electronics 7(272):1–15

    Google Scholar 

  • Ban T, Naviner LAB (2010) A simple fault-tolerant digital voter circuit in TMR nanoarchitectures. In: Proceeding IEEE international NEWCAS conference (NEWCAS), Montreal, QC, Canada, 20–23 June 2010, pp 269–272

  • Chowdary PRV, Babu MN, Subbareddy TV, Reddy BM, Elamaran V (20145) Image processing algorithms for gesture recognition using MATLAB. In: Proceeding IEEE international conference on advanced communication, control and computing technologies (ICACCCT 2014), Ramanathapuram, Tamilnadu, India, 8–10 May 2014, pp 1511–1514

  • Danilov IA, Gorbunov MS, Antonov AA (2014) SET tolerance of 65 nm CMOS majority voters: a comparative study. IEEE Trans Nucl Sci 61(4):1597–1602

    Article  Google Scholar 

  • Dong AX, Gwinn RP, Warner NM, Caylor LM, Doherty MJ (2016) Mitigating bit flips or single event upsets in epilepsy neurostimulators. Epilepsy Behav Case Rep 5:72–74

    Article  Google Scholar 

  • Dubrova E (2013) Fault-tolerant design. Springer, New York

    Book  Google Scholar 

  • Elamaran V, Upadhyay HN (2013) A case study of nanoscale FPGA programmable switches with low power. Int J Eng Technol 5(2):1512–1519

    Google Scholar 

  • Elamaran V, Upadhyay HN (2015a) CMOS VLSI design of low power SRAM cell architectures with new TMR: a layout approach. Asian J Sci Res 8(4):466–477

    Article  Google Scholar 

  • Elamaran V, Upadhyay HN (2015b) Low power digital barrel shifter datapath circuits using Microwind layout editor with high reliability. Asian J Sci Res 8(4):478–489

    Article  Google Scholar 

  • Elamaran V, Upadhyay HN (2017) Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits. Int J Signal Imaging Syst Eng 10(1–2):63–71

    Article  Google Scholar 

  • Elamaran V, Praveen A, Reddy MS, Aditya LV, Suman K (2012) FPGA implementation of spatial image filters using Xilinx System Generator. Proc Eng 38:2244–2249

    Article  Google Scholar 

  • Elamaran V, Hemavathy R, Jayapriya D, Upadhyay HN (2015) Majority function computation using different voter circuits—a comparative study. Int J Pharm Technol 7(3):9764–9773

    Google Scholar 

  • Elamaran V, Narasimhan K, Balaji VS, Chandrasekar M, Upadhyay HN (2017) A case study of fault-tolerant biological systems with MRI images. Biomed Res (India) 28:5247–5251

    Google Scholar 

  • Ferlet-Cavrois V, Massengill LW, Gouker P (2013) Single event transients in digital CMOS—a review. IEEE Trans Nucl Sci 60(3):1767–1790

    Article  Google Scholar 

  • Kshirsagar RV, Patrikar RM (2009) Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits. Microelectron Reliab 49(12):1573–1577

    Article  Google Scholar 

  • Mahatme NN, Gaspard NJ, Assis T, Chatterjee I, Loveless TD, Bhuva BL, Robinson WH, Massengill LW, Wen SJ, Wong R (2014) Kernel-based circuit partition approach to mitigate combinational logic soft errors. IEEE Trans Nucl Sci 61(6):3274–3281

    Article  Google Scholar 

  • Mallavarapu P, Upadhyay HN, Rajkumar G, Elamaran V (2017) Fault-tolerant digital filters on FPGA using hardware redundancy techniques. In: Proceeding IEEE international conference on electronics, communication and aerospace technology (ICECA 2017), Coimbatore, India, 20–22 April 2017, pp 256–259

  • Narasimhan K, Elamaran V (2016) Wavelet-based energy features for diagnosis of melanoma from dermoscopic images. Int J Biomed Eng Technol 20(3):243–252

    Article  Google Scholar 

  • Neale A, Sachdev M (2013) A new SEC-DED error correction code subclass for adjacent MBU tolerance in embedded memory. IEEE Trans Device Mater Reliab 13(1):223–230

    Article  Google Scholar 

  • Oppenheim AV, Schafer RW (2010) Discrete-time signal processing. 3rd Edition, Pearson Education India

  • Polian I, Hayes JP (2011) Selective hardening: toward cost-effective error tolerance. IEEE Des Test Comput 28(3):54–63

    Article  Google Scholar 

  • Polian I, Reddy SM, Becker B (2008) Scalable calculation of logical masking effects for selective hardening against soft errors. In: Proceeding IEEE computer society annual symposium on VLSI, Montpellier, France, April 7–9, 2008, pp 257–262

  • Radhakrishnan S, Nirmalraj T, Ashwin S, Elamaran V, Karn RK (2018) Fault tolerant carry save adders—a NMR configuration approach. In: Proceeding IEEE international conference on control, power, communication and computing technologies (ICCPCCT), Kannur, India, 23–24 March 2018, pp 210–215

  • Rastogi A, Agarawal M, Gupta B (2009) SEU MITIGATION-using 1/3 rate convolution coding. In: Proceeding IEEE international conference on computer science and information technology (ICCSIT 2009), Beijing, China, 8–11 August 2009, pp 180–183

  • Ratter D (2004) FPGAs on Mars. Xcell J 50:8–12

    Google Scholar 

  • Reviriego P, Maestro JA (2009) Study of the effects of multibit error correction codes on the reliability of memories in the presence of MBUs. IEEE Trans Device Mater Reliab 9(1):31–39

    Article  Google Scholar 

  • Reviriego P, Maestro JA, Lopez-Calle I, De Agapito JA (2011) Soft error tolerant Infinite Impulse Response filters using reduced precision replicas. In: Proceedings European conference on radiation and its effects on components and systems (RADECS), Sevilla, Spain, 19–23 September, 2011, pp 19–23

  • Reviriego P, Ruano O, Maestro JA (2012) Implementing concurrent error detection in infinite-impulse-response filters. IEEE Trans Circuits Syst II Express Briefs 59(9):583–586

    Article  Google Scholar 

  • Ruano O, Maestro JA, Reviriego P (2011) A fast and efficient technique to apply selective TMR through optimization. Microelctr Reliab 51(12):2388–2401

    Article  Google Scholar 

  • Sasi G, Ashwin S, Rajkumar G, Elamaran V, Upadhyay HN (2018) Minimal test coverage of SSFs for the majority voters of TMR configuration. In: Proceedings IEEE international conference on control, power, communication and computing technologies (ICCPCCT), Kannur, India, 23–24 March 2018, pp 256–259

  • Shim B, Sridhara SR, Shanbhag NR (2004) Reliable low-power digital signal processing via reduced precision redundancy. Trans Very Large Scale Integr VLSI Syst 12(5):497–510

    Article  Google Scholar 

  • Sicard E (2006) Microwind and Dsch version 3.1. INSA Toulouse

  • Singh J, Mathew J, Hosseinabady M, Pradhan DK (2007) Single event upset detection and correction. In: Proc. International conference on information technology (ICIT 2007), Orissa, India, 17–20 December, 2007, pp 13–18

  • Subramani SHH, Rajesh KSSK, Elamaran V (2014) Low energy, low power adder logic cells: a CMOS VLSI implementation. Asian J Sci Res 7(2):248–255

    Article  Google Scholar 

  • Tausch HJ (2009) Simplified birthday statistics and hamming EDAC. IEEE Trans Nucl Sci 56(2):474–478

    Article  MathSciNet  Google Scholar 

  • Xuan S, Li N (2014) SEU hardened placement and routing based on slack reduction. IEEE Trans Nucl Sci 61(5):2741–2744

    Article  Google Scholar 

  • Zhu M, Xiao L, Li S, Zhang Y (2010) Efficient two-dimensional error codes for multiple bit upsets mitigation in memory. In: Proceedings IEEE international symposium on defect and fault tolerance in VLSI systems (DFT), Kyoto, Japan, 6–8 October 2010, pp 129–135

  • Zhu M, Xiao LY, Liu C, Wei ZJ (2011) Reliability of memories protected by multibit error correction codes against MBUs. IEEE Trans Nucl Sci 58(1):289–329

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of ECE, V.S.B. Engineering College, Karur, Tamil Nadu, India

    V. N. Senthil Kumaran

  2. Department of ECE, Sreyas Institute of Engineering and Technology, Hyderabad, India

    Shaik Fairooz

  3. Department of Electrical and Communication Engineering, College of Engineering, National University of Science and Technology, Muscat, Sultanate of Oman

    R. Krishna Priya

  4. Department of ECE, Sri Indu Institute of Engineering and Technology, Hyderabad, India

    Dayadi Lakshmaiah

  5. Department of EEE, GIET University, Gunupur, Odisha, India

    J. V. Subramanyam

  6. School of EEE, SASTRA Deemed University, Thanjavur, India

    V. S. Balaji & V. Elamaran

Authors
  1. V. N. Senthil Kumaran
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shaik Fairooz
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. R. Krishna Priya
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Dayadi Lakshmaiah
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. J. V. Subramanyam
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. V. S. Balaji
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. V. Elamaran
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to V. S. Balaji.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kumaran, V.N.S., Fairooz, S., Priya, R.K. et al. NMR configurations with novel majority voter circuits to mask multiple module faults. J Ambient Intell Human Comput (2021). https://doi.org/10.1007/s12652-021-03074-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s12652-021-03074-3

Keywords

Search

Navigation