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FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node

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Abstract

Stress engineering is one of the best techniques to enhance the potential of a device. In the first phase of this work, the impact of stress on the physical and electrical performance of FinFET based inverter is investigated using 2D and 1D stress mapping techniques. Electrons and holes mobility enhancements are presented in the sidewall fins of <100> and < 110> direction respectively, by resulting tensile stress in n-FinFET and compressive stress in p-FinFET. According to the sidewall orientation (<100 > or < 110>), the amount of mobility enhancement of both the electrons and holes are resulting in more than 100% (>100%) and less than 25% (<25%) respectively. In the second phase, Design Technique Co-Optimization (DTCO) method is approached in inverter standard cells generation to enable the VLSI digital system design flow based on standard cells using FinFET. FinFET-based inverters at 7 nm technology nodes is designed using the GTS TCAD framework. The optimal electrical characteristics such as current density, throughput delay, average power dissipation, and switching energy are presented with optimal design.

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References

  1. Takagi S, Tezuka T, Irisawa T, Nakaharai S, Numata T, Usuda K, Sugiyama N, Shichijo M, Nakane R, Sugahara S (2007) Device structures and carrier transport properties of advanced CMOS using high mobility channels. Solid State Electronics 51:526–536

    Article  CAS  Google Scholar 

  2. Maiti CK (2017) Introducing technology computer-aided design (TCAD) - fundamentals, simulations, and applications. Pan Stanford Publishing Ltd., Singapore

    Book  Google Scholar 

  3. Dash T P, Jena J, Mohapatra E, Dey S, Das S, Maiti C K (2019) Role of stress/strain mapping in advanced CMOS process technology nodes. IEEE international conference on device integrated circuits (DevIC-2019): 21-25

  4. Pidin S, Mori T, Inoue K, Fukuta S, Itoh N, Mutoh E, Ohkoshi K, Nakamura R, Kobayashi K, Kawamura K, Saiki T, Fukuyama S, Satoh S, Kase M, Hashimoto K (2004) A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films. In IEEE Electron Devices Meeting IEDM-2004:213–216

    Google Scholar 

  5. Nouri F, Verheyen P, Washington L, Moroz V, De Wolf I, Kawaguchi M, Biesemans S, Schreutelkamp R, Kim Y, Shen M, Xu X, Rooyackers R, Jurczak M, Eneman G, De Meyer K, Smith L, Pramanik D, Forstner H, Thirupapuliyur S, Higashi GS (2004) A systematic study of trade-offs in engineering a locally strained pMOSFET. IEEE Electron Devices Meeting (IEDM-2004):1055–1058

  6. Wang J, Tateshita Y, Yamakawa S, Nagano K, Hirano T, Kikuchi Y, Y. Miyanami, Yamaguchi S, Tai K, Yamamoto R, Kanda S, Kimura T, Kugimiya K, Tsukamoto M, Wakabayashi H, Tagawa Y, Iwamoto H, Ohno T, Saito M, Kadomura S, Nagashima N (2007) Novel channel-stress enhancement technology with eSiGe S/D and recessed channel on damascene gate process. IEEE Symposium on VLSI Technology-2007: 46–47

  7. Madan A, Samudra G, Yeo YC (2008) Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors. J Appl Phys 104:84505

    Article  Google Scholar 

  8. Numata T, Irisawa T, Tezuka T, Koga J, Hirashita N, Usuda K, Toyoda E, Miyamura Y, Sugiyama N, Shin-ichi T (2004) Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters. IEEE Electron Devices Meeting IDEM-2007:177–180

    Google Scholar 

  9. Flachowsky S, Illgen R, Herrmann T, Baldauf T, Wei A, Hontschel J, Klix W, Stenzel R, Horstmann M (2010) Stress memorization technique for n-MOSFETs:where is the stress memorized? Ultimate integration on Silicon-2010:149–152

  10. Cirne K H and Gimenez S P (2009) Layout design of CMOS inverters with circular and conventional gate MOSFETs by using IC station mentor proc. 9th microelectronics students forum, SBMicro 2009 (Natal, Brazil). Available: https://sbmicro.org.br/sforum-eventos/sforum2009/cirne.pdf

  11. Silvaco Inc (2018) Silvaco VictoryCell, user manual

    Google Scholar 

  12. Silvaco Inc (2018) VictoryStress user manual

  13. Yang M, Chan Victor WC, Chan KK, Leathen S, Fried David M, Stathis JH, Chou AI, Gusev E, Ott JA, Burns LE, Fischetti MV, Ieong M (2006) Hybrid-orientation technology (HOT):opportunities and challenges. IEEE Transactions on Electron Devices 53:965–978

    Article  Google Scholar 

  14. Iyengar V V, Kottantharayil A, Tranjan F M, Jurczak M, Meyer K. De (2007) Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on mobility. IEEE Transactions on Electron Devices 54:1177–1184

  15. Thathachary AV, Lavallee G, Cantoro M, Bhuwalka KK, Heo Y-C, Maeda S, Datta S (2015) Impact of sidewall passivation and channel composition on InxGa1-xAs FinFET performance. IEEE Electron Device Letters 36:117–119

    Article  CAS  Google Scholar 

  16. Young C D, Akarvardar K, Bersuker G, Ok I, Ngai T, Ang K-W, Hobbs C, Kirsch P, R. Jammy R (2011) Performance and reliability investigation of (110) and (100) sidewall oriented MugFETs. International Semiconductor Device Research Symposium (ISDRS-2011):1

  17. Kurinec S K (2020) Nanoscale Materials Engineering for Microelectronics. In :A. Parker, L. Lunardi (eds) Women in Microelectronics, Springer, Cham

  18. Bari S, De D, Sarkar A (2015) Effect of gate engineering in JLSRG MOSFET to suppress SCEs: an analytical study. Physica E: Low-dimensional Systems and Nanostructures 67:143–151

    Article  CAS  Google Scholar 

  19. Baral B, Das AK, De D, Sarkar A (2016) An analytical model of triple-material double-gate metal–oxide–semiconductor field-effect transistor to suppress short-channel effects. International Journal of Numerical Modelling: Electronic Networks, Devices

  20. Garcia-Loureiro AJ, Seoane N, Aldegunde M, Valin R, Asenov A, Martinez A, Kalna K (2011) Implementation of the density gradient quantum corrections for 3-D simulations of multigate Nanoscaled transistors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30:841–851

    Article  Google Scholar 

  21. GTS Framework, MINIMOS-NT user manual (2020)

    Google Scholar 

  22. Kernstock C, Stanojevic Z, Baumgartner O, Karner M (2015) Layout-based TCAD device model generation. In IEEE international conference on simulation of semiconductor processes and devices: 198–201

  23. Wu H, Luo W, Zhou H, Si M, Zhang J, Ye P D (2015) First experimental demonstration of Ge 3D FinFET CMOS circuits. Symposium on VLSI technology (VLSI Technology-2015):T58-T59

  24. Bir GL, Pikus GE (1974) Symmetry and strain-induced effects in semiconductors. Wiley, A Halsted Press

    Google Scholar 

  25. Silvaco Inc(2016) VictoryProcess User’s manual

  26. Xie R, Montanini P, Akarvardar K, Tripathi N, Haran B, Johnson S, Hook T, Hamieh B, Corliss D, Wang J, Miao X, Sporre J, Fronheiser J, Loubet N, Sung M, Sieg S, Mochizuki S, Prindle C, Seo S, Greene A, Shearer J, Labonte A, Fan S, Liebmann L, Chao R, Arceo A, Chung K, Cheon K, Adusumilli P, Amanapu H P, Bi Z, Cha J, Chen H.-C, Conti R, Galatage R, Gluschenkov O, Kamineni V, Kim K, Lee C, Lie F, Liu Z, Mehta S, E. Miller E, Niimi H, Niu C, Park C, Park D, Raymond M, Sahu B, Sankarapandian M, Siddiqui S, Southwick R, Sun L, Surisetty C, Tsai S, Whang S, Xu P, Xu Y, Yeh C, P. Zeitzoff P, Zhang J, Li J, Demarest J, Arnold J, Canaperi D, Dunn D, Felix N, Gupta D, Jagannathan H, Kanakasabapathy S, Kleemeier W, Labelle C, Mottura M, Oldiges P, Skordas S, Standaert T, Yamashita T, Colburn M, Na M, Paruchuri V, Lian S, Divakaruni R, Gow T, Lee S, Knorr A, Bu H, Khare M (2016) 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels. In IEEE Electron Devices Meeting (IEDM-2016): 2.7.1–2.7.4

  27. Dash TP, Dey S, Das S, Jena J, Mahapatra E, Maiti CK (2020) Source/drain stressor Design for Advanced Devices at 7nm technology nodes. Nanoscience & Nanotechnology-Asia 10:447–456

    Article  CAS  Google Scholar 

  28. Gendron-Hansen A, Korablev K, Chakarov I, Egley J, Cho J, Benistant F (2015) TCAD analysis of FinFET stress engineering for CMOS technology scaling. International conference on simulation of semiconductor processes and devices (SISPAD-2015). Washington, DC, pp 417–420

    Chapter  Google Scholar 

  29. Maiti C K, Maiti T K (2012) Strain-engineered MOSFETs, CRC Press

  30. Shin K, Lauderdale T, King T-J (2005) Effect of tensile capping layer on 3-D stress profiles in FinFET channels. 63rd device research conference digest (DRC-2005). Santa Barbara, CA, pp 201–202

    Chapter  Google Scholar 

  31. Cho J, Geelhaar F, Rana U, Vanamurthy L, Sporer R, Benistant F (2017) TCAD analysis of SiGe channel FinFET devices. In international conference on simulation of semiconductor processes and devices (SISPAD-2017), Kamakura: 357-360

  32. Smith CS (1954) Piezoresistance effect in germanium and silicon. Physical review journals 94:42–49

    Article  CAS  Google Scholar 

  33. Kanda Y (1982) Graphical representation of the Piezoresistance coefficients in silicon. IEEE Transactions on Electron Devices 29:64–70

    Article  Google Scholar 

  34. Moroz V, Lin X W, Asenov P, D. Sherlekar, Choi M, Sponton L, Melvin L S, Lee J, Cheng B, Nannipieri A, Huang J, Jones S (2020) DTCO Launches Moore’s Law Over the Feature Scaling Wall. In Proc. Intl. Electron Devices Meeting (IEDM): 913–916

  35. Deyasi A, Sarkar A (2018) Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method. Int J Electron 105:2144–2159

    Article  CAS  Google Scholar 

  36. Biswal SM, Baral B, De D, Sarkar A (2015) Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE. Superlattice Microst 82:103–112

    Article  CAS  Google Scholar 

  37. Dash TP, Jena J, Mohapatra E, Dey S, Das S, Maiti CK (2019) Stress-induced variability studies in tri-gate FinFETs with source/drain stressor at 7nm technology nodes. J Electron Mater 48:5348–5362

    Article  CAS  Google Scholar 

  38. Lombardi C, Manzini S, Saporito A, Vanzi M (1988) A physically based mobility model for numerical simulation of nonplanar devices. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7:1164–1171

    Article  Google Scholar 

  39. Reggiani S, Gnani E, Gnudi A, Rudan M, Baccarani G (2007) Low-field electron mobility model for ultrathin-body SOI and double-gate MOSFETs with extremely small silicon thicknesses. IEEE Transactions on Electron Devices 54:2204–2212

    Article  CAS  Google Scholar 

  40. Erlebach A, Lee K H, Lee H, Bufler F M (2016) Empirical ballistic mobility model for drift-diffusion simulation. In 46th European solid-state device research conference (ESSDERC): 420–423

  41. Stanojevic Z, Baumgartner O, Mitterbauer F, Demel H, Kernstock C, Karner M, Eyert V, France-Lanord A, Saxe P, Freeman C, Wimmer E (2015) Physical modeling – a new paradigm in device simulation. In IEEE Electron Devices Meeting IEDM-2015:5.1.1–5.1.4

    Google Scholar 

  42. Stanojevic Z, Karner M, Baumgartner O, Karner HW, Kernstock C, Demel H, F. Mitterbauer F (2016) Phase-space solution of the subband Boltzmann transport equation for nano-scale TCAD. In International Conference on Simulation of Semiconductor Processes and Devices (SISPAD-2016): 65–67

  43. Biswal SM, Baral B, De D, Sarkar A (2019) Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire (nw) tunnel FET. Microsyst Technol 25:1855–1861

    Article  CAS  Google Scholar 

  44. Jena J, Das S, Mohapatra E, Nanda J, Dash T P (2021) Performance analysis of FinFET based inverter at 7nm technology node using TCAD simulation. IEEE international conference on devices for integrated circuit (DevIC-2021):143-147

  45. Natarajan S, Agostinelli M, Akbar S, Bost M, Bowonder A, Chikarmane V, Chouksey S, Dasgupta A, Fischer K, Fu Q, Ghani T, Giles M, Govindaraju S, Grover R, Han W, Hanken D, Haralson E, Haran M, Heckscher M, Heussner R, Jain P, James R, Jhaveri R, Jin I, Kam H, Karl E, Kenyon C, Liu M, Luo Y, Mehandru R, Morarka S, Neiberg L, Packan P, Paliwal A, Parker C, Patel P, Patel R, Pelto C, Pipes L, Plekhanov P, Prince M, Rajamani S, Sandford J, Sell B, Sivakumar S, Smith P, Son B, Tone K, Troeger T, Wiedemer J, Yang M, Zhang K (2016) A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size. In IEEE international Electron devices meeting (IEDM-2015): 3.7.1-3.7.3

  46. Moroz V, Huang J, Arghavani R (2016) Transistor design for 5nm and beyond: slowing down electrons to speed up transistors. In 17th international symposium on quality electronic design (ISQED): 278-283

  47. Biswas K, Sarkar A, Sarkar CK (2016) Impact of fin width scaling on RF/analog performance of junctionless accumulation-mode bulk FinFET. ACM Journal on Emerging Technologies in Computing Systems (JETC) 12:1–12

    Article  Google Scholar 

  48. Guo X, Verma V, Gonzalez-Guerrero P, Mosanu S, Stan MR (2017) Back to the future: digital circuit design in the FinFET era. Journal of Low Power Electronics 13:338–355

    Article  Google Scholar 

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Conceptualization: Jhansirani Jena and Taraprasanna Dash; Methodology: Jhansirani Jena, Eleena Mohapatra; Formal analysis and investigation: Jhansirani Jena and Sanghamita Das; Writing - original draft preparation: Jhansirani Jena, Taraprasanna Dash,; Writing - review and editing: Eleena Mohapatra, Devika Jena,; Supervision: Taraprasanna Dash.

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Jena, J., Jena, D., Mohapatra, E. et al. FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node. Silicon 14, 10781–10794 (2022). https://doi.org/10.1007/s12633-022-01812-6

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  • DOI: https://doi.org/10.1007/s12633-022-01812-6

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