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Performance Analysis of Hetero Gate Oxide with Work Function Engineering Based SC-TFET with Impact of ITCs

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Abstract

This manuscript illustrates the effects of temperature (T) and Interface trap charges (ITCs) on proposed device (Hetero Gate Oxide-Dual Work function- Step Channel Tunnel Field Effect Transistor (HGO-DW-SC-TFET)). Some crucial device performance parameters, such as Vth, ION, IOFF, SS, ION/IOFF are improved when hetero gate oxide with dual work-function is implemented on HGO-DW-SC-TFET. Performance analysis of the proposed device has been done by examine the DC, Analog/Radio Frequency, and linearity figure of merits (FOMs) at various temperatures and ITCs, which are allocated at the insulator and semiconductor interface. OFF-State analysis of the HGO-DW-SC-TFET performed by considering various models like BTBT, SRH, and TAT, which significantly affect the device performance for T variation. To examine analog/RF performance of simulated devices, Gate-Drain Capacitance (Cgd), Gate-Source Capacitance (Cgs), Trans-conductance (gm1), Gain-Bandwidth -Product (GBP), Trans-conductance-Frequency-Product (TFP), Cutoff-Frequency (fT), Trans-conductance-Generation-Factor (TGF), Transit Time (TT) are analyzed with consideration of T and ITCs variations. Similarly, linearity FOMs of proposed device are investigated in terms of derivatives of trans-conductance (gm2, gm3), Voltage-Intercept-Points (V IP2, V IP3), Input-Intercept-Point (IIP3), and Inter-Modulation-Distortion (IMD3).

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References

  1. Iwai H (2009) Si mosfet roadmap for 22nm and beyond. In: 2009 4th international conference on computers and devices for communication (CODEC). IEEE, pp 1–4

  2. Tsai M-H, Ma T-P (1994) The impact of device scaling on the current fluctuations in mosfet’s. IEEE Transactions on Electron Devices 41(11):2061–2068

    Article  CAS  Google Scholar 

  3. Sun S-W, Tsui PG (1995) Limitation of cmos supply-voltage scaling by mosfet threshold-voltage variation. IEEE Journal of Solid-State Circuits 30(8):947–949

    Article  Google Scholar 

  4. Koswatta SO, Lundstrom MS, Nikonov DE (2009) Performance comparison between pin tunneling transistors and conventional mosfets. IEEE Transactions on Electron Devices 56(3):456–465

    Article  CAS  Google Scholar 

  5. Avci UE, Morris DH, Young IA (2015) Tunnel field-effect transistors: Prospects and challenges. IEEE Journal of the Electron Devices Society 3(3):88–95

    Article  Google Scholar 

  6. Choi WY, Park B-G, Lee JD, Liu T-JK (2007) Tunneling field-effect transistors (tfets) with subthreshold swing (ss) less than 60 mv/dec. IEEE Electron Device Letters 28(8):743–745

    Article  CAS  Google Scholar 

  7. Wu J, Min J, Taur Y (2015) Short-channel effects in tunnel fets. IEEE Transactions on Electron Devices 62(9):3019–3024

    Article  Google Scholar 

  8. Justeena AN, Nirmal D, Gracia D (2017) Design and analysis of tunnel fet using high k dielectric materials. In: 2017 international conference on innovations in electrical, electronics, instrumentation and media technology (ICEEIMT). IEEE, pp 177– 180

  9. Boucart K, Ionescu AM (2006) Double gate tunnel fet with ultrathin silicon body and high-k gate dielectric. In: 2006 European Solid-State Device Research Conference. IEEE, pp 383–386

  10. Sangeetha G, Khan TA, Hameed TS (2016) Sige/si heterojunction tfet for analog signal applications. In: 2016 international conference on next generation intelligent systems (ICNGIS). IEEE, pp 1–6

  11. Yadav DS, Sharma D, Tirkey S, Soni D, G Sharma D, Bajpai S, Sharma N (2017) A comparative study of gap/sige hetero junction double gate tunnel field effect transistor. In: 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS). IEEE, pp 195–199

  12. Madan J, Bisht SS, Chaujar R (2018) Heterojunction dg-tfet-analysis of different source material for improved intermodulation. In: 2018 2nd international conference on trends in electronics and informatics (ICOEI). IEEE, pp 1080–1084

  13. Yadav DS, Sharma D, Raad BR, Bajaj V (2016) Impactful study of dual work function, underlap and hetero gate dielectric on tfet with different drain doping profile for high frequency performance estimation and optimization. Superlattice Microst 96:36– 46

    Article  CAS  Google Scholar 

  14. Yadav DS, Sharma D, Raad BR, Bajaj V (2016) Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis. In: 2016 international conference on advanced communication control and computing technologies (ICACCCT). IEEE, pp 26–29

  15. Nigam K, Kondekar P, Sharma D (2016) Approach for ambipolar behaviour suppression in tunnel fet by workfunction engineering. Micro & Nano Letters 11(8):460–464

    Article  CAS  Google Scholar 

  16. Soni D, Sharma D, Yadav S, Aslam M, Yadav DS, Sharma N (2017) Gate metal work function engineering for the improvement of electrostatic behaviour of doped tunnel field effect transistor. In: 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS). IEEE, pp 190–194

  17. Singh P, Yadav DS (2021) Design and investigation of f-shaped tunnel fet with enhanced analog/rf parameters, Silicon. https://doi.org/10.1007/s12633-021-01420-w

  18. Kumar S, Yadav DS, Saraswat S, Parmar N, Sharma R, Kumar A (2020) A novel step-channel tfet for better subthreshold swing and improved analog/rf characteristics. In: 2020 IEEE international students’ conference on electrical, electronics and computer science (SCEECS). IEEE, pp 1–6

  19. Ghosh S, Koley K, Sarkar CK (2016) Effect of temperature variability on rf performance of germanium ptfet. In: 2016 3rd international conference on devices, circuits and systems (ICDCS). IEEE, pp 304–307

  20. Rahi SB, Ghosh B, Bishnoi B (2015) Temperature effect on hetero structure junctionless tunnel fet. Journal of Semiconductors 36(3):034002

    Article  Google Scholar 

  21. Liu Y, Chen D, Dong K, Lu H, Zhang R, Zheng Y, Zhu Z, Wei G, Lin Z (2018) Temperature dependence of the energy band diagram of algan/gan heterostructure. Advances in Condensed Matter Physics

  22. Singh P, Samajdar DP, Yadav DS (2021) A low power single gate l-shaped tfet for high frequency application. In: 2021 6th international conference for convergence in technology (I2CT). IEEE, pp 1–6

  23. Venkatesh P, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Impact of interface trap charges on performance of electrically doped tunnel fet with heterogeneous gate dielectric. IEEE Transactions on Device and Materials Reliability 17(1):245–252

    Article  CAS  Google Scholar 

  24. Das B, Bhowmick B (2021) Effect of curie temperature on ferro electric tunnel fet and its rf/analog performance. In: IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 68, no. 4, pp. 1437–1441. https://doi.org/10.1109/TUFFC.2020.3033761

  25. Pon A, Tulasi KSVP, Ramesh R (2019) Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel fet. AEU-International Journal of Electronics and Communications 102:1–8

    Google Scholar 

  26. Gupta S, Sharma D, Soni D, Yadav S, Aslam M, Yadav DS, Nigam K, Sharma N (2018) Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability. Micro & Nano Letters 13(8):1192–1196

    Article  CAS  Google Scholar 

  27. Suk SD, Lee S-Y, Kim S-M, Yoon E-J, Kim M-S, Li M, Oh CW, Yeo KH, Kim SH, Shin D-S et al (2005) High performance 5nm radius twin silicon nanowire mosfet (tsnwfet): fabrication on bulk si wafer, characteristics, and reliability. In: IEEE Internationalelectron devices meeting 2005. IEDM Technical Digest. IEEE, pp 717–720

  28. Chander S, Sinha SK, Kumar S, Singh PK, Baral K, Singh K, Jit S (2017) Performance evaluation of heterojunction soi-tunnel fet with temperature. In: 2017 14th IEEE India council international conference (INDICON). IEEE, pp 1–5

  29. Green E (2014) Temperature dependence of semiconductor conductivity

  30. Yadav DS, Sharma D, Agrawal R, Prajapati G, Tirkey S, Raad BR, Bajaj V (2017) Temperature based performance analysis of doping-less tunnel field effect transistor. In: 2017 international conference on information, communication, instrumentation and control (ICICIC). IEEE, pp 1–6

  31. Sajjad RN, Antoniadis D (2016) A compact model for tunnel fet for all operation regimes including trap assisted tunneling. In: 2016 74th annual device research conference (DRC). IEEE, pp 1–2

  32. Sajjad RN, Chern W, Hoyt JL, Antoniadis DA (2016) Trap assisted tunneling and its effect on subthreshold swing of tunnel fets. IEEE Transactions on Electron Devices 63(11):4380– 4387

    Article  CAS  Google Scholar 

  33. Smets Q, Verhulst AS, Simoen E, Gundlach D, Richter C, Collaert N, Heyns MM (2017) Calibration of bulk trap-assisted tunneling and shockley–read–hall currents and impact on ingaas tunnel-fets. IEEE Transactions on Electron Devices 64(9):3622–3626

    Article  CAS  Google Scholar 

  34. Singh P, Yadav DS (2021) Impact of temperature on analog/rf, linearity and reliability performance metrics of tunnel fet with ultra-thin source region. Applied Physics A 127(9):1–15

    Article  Google Scholar 

  35. Gupta AK, Raman A, Kumar N (2019) Design and investigation of a novel charge plasma-based core-shell ring-tfet: analog and linearity analysis. IEEE Transactions on Electron Devices 66(8):3506–3512

    Article  CAS  Google Scholar 

  36. Biswal SM, Baral B, De D (2017) Analog/radiofrequency and linearity performance of staggered heterojunction nanowire (nw) tunnel fet for low power application. In: 2017 devices for integrated circuit (DevIC). IEEE, pp 441–445

  37. Chandan BV, Nigam K, Pandey S, Sharma D, Kondekar P (2017) Temperature sensitivity analysis on analog/rf and linearity metrics of electrically doped tunnel fet. In: 2017 conference on information and communication technology (CICT). IEEE, pp 1–5

  38. Singh P, Yadav DS (2021) Impactful study of f-shaped tunnel fet, Silicon. https://doi.org/10.1007/s12633-021-01319-6

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Acknowledgements

The authors would like to thank Dr. Dip Prakash Samajdar from Department of Electronics and Communication Engineering, PDPM Indian Institute of Information Technology, Design & Manufacturing, Jabalpur, Madhya Pradesh, India for providing valuable suggestions and support to carry out this research work.

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Manshi Kamal: Conceptualization, data curation, formal analysis, methodology, investigation, writing – original draft. Dharmendra Singh Yadav: Supervision, validation, visualization, writing – review & editing

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Correspondence to Dharmendra Singh Yadav.

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Yadav, D.S., Kamal, M. Performance Analysis of Hetero Gate Oxide with Work Function Engineering Based SC-TFET with Impact of ITCs. Silicon 14, 11429–11441 (2022). https://doi.org/10.1007/s12633-022-01792-7

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