Skip to main content
SpringerLink
Log in

Recent Trends in Novel Semiconductor Devices

  • Review Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

The VLSI industry has grown a lot for several decades. The Packing density of integrated circuits has been increased without compromising the functionality. Scaling of semiconductor devices, improvements in process technology and the development of new device designs are the key to this. Starting from the planar MOSFETs to novel multigate transistors, semiconductor devices have a history of many decades. There is a need for extensive exploration in order to determine the best suited semiconductor device for a given technology node. A brief overview of the transition from the planar MOSFET to the novel semiconductor devices and a comparative study of various novel semiconductor devices viz. FinFET, Gate all around FET, Vertical Nanowire and Nanosheet FET are presented in this paper. Optimization of the device configuration and improvements in device design/technology are also reviewed. A review of the device comparison on the basis of various device performance parameters such as subthreshold slope, On-Off current ratio, ease of fabrication, process variations and impact of scaling on figure of merits is presented in this paper.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

Not applicable.

Code Availability

Not applicable.

References

  1. Yan RH, Ourmazd A, Lee KF (1992) Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Transactions on Electron Devices 39:1704–1710. https://doi.org/10.1109/VTSA.2011.5872206

    Article  CAS  Google Scholar 

  2. Kuhn K. J. (2011) CMOS scaling for the 22nm node and beyond: Device physics and technology. International Symposium on VLSI Technology, Systems and Applications :1–2

  3. Roy K, Mukhopadhyay S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91:305–327

    Article  CAS  Google Scholar 

  4. Frank DJ et al (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89:259–287. https://doi.org/10.1109/ASQED.2009.5206287

    Article  CAS  Google Scholar 

  5. Cheng H.W, Hwang C. H, Li Y (2009) Propagation delay dependence on channel fins and geometry aspect ratio of 16-nm multi-gate MOSFET inverter. 1st Asia Symposium on Quality Electronic Design :122–125

  6. Hu C. H. C. (1996) Gate oxide scaling limits and projection. IEEE International Electron Devices Meeting Technical Digest :8–11

  7. Yeo YC, King T, Hu C (2003) MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations. IEEE Transactions on Electron Devices 50:1027–1035

    Article  CAS  Google Scholar 

  8. Chen J, Chan TY, Chen IC, Ko PK, Hu C (1987) Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Letters 8:515–517

    Article  Google Scholar 

  9. Thompson S, Packan P, Bohr M (1998) MOS Scaling : Transistor Challenges for the 21st Century. Intel Technology Journal :1–19

  10. Mohapatra N.R, Dutta A, Desai M. P, Rao V. R (2001) Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics. Fourteenth International Conference on VLSI Design :6–9

  11. Maitra K, Bhat N, Member S (2004) Impact of gate-to-source / drain overlap length on 80-nm CMOS circuit performance. IEEE Transactions on Electron Devices 51(3):409–414

    Article  Google Scholar 

  12. Suzuki K, Tanaka T, Tosaka Y, Horie H, Arimoto Y (1993) Scaling theory for double-gate SOI MOSFET’s. IEEE Transactions on Electron Devices 40:2326–2329

    Article  CAS  Google Scholar 

  13. Chang L et al (2003) Extremely scaled silicon nano-CMOS devices. Proc IEEE 91:1860–1872

    Article  CAS  Google Scholar 

  14. Mishra P, Muttreja A, Jha NK (2008) Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. IEEE International Symposium on Nanoscale Architectures 5:77–84

    Google Scholar 

  15. Choi Y-K et al (1999) Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. IEEE International Electron Devices Meeting Technical Digest 99:919–921

    Google Scholar 

  16. Hisamoto D, Kaga TA. (1989). IEEE International Electron Devices Meeting Technical Digest :833–836

  17. Hisamoto D et al (2000) FinFET — a self-aligned double-gate MOSFET. IEEE Transactions on Electron Devices 47(12):2320–2325. https://doi.org/10.1109/IEDM.1998.746385

    Article  CAS  Google Scholar 

  18. Wong H.-S.P, Frank D. J, Solomon P. M (1998) Device design considerations for double-gate, ground-plane, and\nsingle-gated ultra-thin SOI MOSFET’s at the 25 nm channel length\ngeneration. IEEE International Electron Devices Meeting Technical Digest :407–410

  19. Schwarz S. A, Russek S. E(1983) Overcoming silicon scaling barriers with double-gate and FinFET Technology. Technical report IEEE Circuits and Devices Magazine 30:1634–1639

  20. Sudha D.F Sudha, D. (2016) FinFET- One Scale up CMOS : Resolving Scaling Issues. IEEE 3rd International Conference on Computing for Sustainable Global Development (INDIACom) :1183–1187

  21. Datta A et al (2007) Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE Transactions on Computer-aided Design of Integrated circuits and Systems 26(11):957–1966

    Article  Google Scholar 

  22. Yoon J et al (2015) Junction design strategy for Si bulk FinFETs for system-on-Chip applications down to the 7-nm node. IEEE Electron Device Letters 36(10):994–996

    Article  Google Scholar 

  23. Hoffmann T. et al. (2005) GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices. IEEE International Electron Devices Meeting Technical Digest :0–3

  24. Yoon JS, Jeong J, Lee S, Baek RH (2020) Sensitivity of source/drain critical dimension variations for Sub-5-nm node fin and Nanosheet FETs. IEEE Transactions on Electron Devices 67(1):258–262. https://doi.org/10.1109/TED.2019.2951671

    Article  CAS  Google Scholar 

  25. Mochizuki S et al (2019) Advanced arsenic doped epitaxial growth for source drain extension formation in scaled FinFET devices. IEEE International Electron Devices Meeting Technical Digest 35(2):1–35.2.4. https://doi.org/10.1109/IEDM.2018.8614543

    Article  Google Scholar 

  26. Lu P et al (2021) Source/drain extension doping engineering for variability suppression and performance enhancement in 3-nm node FinFETs. IEEE Transactions on Electron Devices 68(3):1352–1357. https://doi.org/10.1109/TED.2021.3052432

    Article  CAS  Google Scholar 

  27. Mohapatra, N. R., Desai, M. P., Narendra, S. G. & Rao, V. R. (2001) The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance. In Proceedings of the 31st European Solid-State Device Research Conference (ESSDERC) :239–242

  28. Field HD, Kim H, Member S, Cho H, De Finfet AA (2020) High-voltage drain-extended FinFET with a high-K dielectric Field plate. IEEE Transactions on Electron Devices 67(3):1077–1084

    Article  Google Scholar 

  29. Miyashita, T. et al. (2015) High voltage I/O FinFET device optimization for 16nm system-on-a-chip. IEEE Symposium on VLSI Technology :T152–T153

  30. Technology S et al (2017) Simulation-based study of hybrid fin / planar LDMOS design for FinFET-based. IEEE Transactions on Electron Devices 64(10):4193–4199

    Article  Google Scholar 

  31. Shrivastava M, Gossner H, Rao VR (2012) A novel drain-extended FinFET device for high-voltage high-speed applications. IEEE Electron Device Letters 33(10):1432–1434

    Article  CAS  Google Scholar 

  32. Shrivastava M, Baghini MS., Sharma D. K, Rao V. R (2010) A novel bottom spacer FinFET structure for improved short-channel, power-delay, and thermal performance. IEEE Transactions on Electron Devices 57(6):1287–1294 . https://doi.org/10.1109/IEDM.2017.8268472

  33. Auth, C. et al. (2018) A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects. IEEE International Electron Devices Meeting Technical Digest :29.1.1–29.1.4

  34. Paul M et al (2019) Drain-extended FinFET with embedded SCR (DeFinFET-SCR) for high-voltage ESD protection and self-protected designs. IEEE Transactions on Electron Devices 66(12):5072–5079. https://doi.org/10.1109/TED.2019.2949126

    Article  CAS  Google Scholar 

  35. Monishmurali M. and Shrivastava M.,(2021) “A Novel High Voltage Drain Extended FinFET SCR for SoC Applications,” in Proceedings of IEEE Int. Reliab. Phys. Symp :2–5. https://doi.org/10.1109/IRPS46558.2021.9405194

  36. Verheyen, P. et al. (2005) 25% Drive current improvement for p-type Multiple Gate FET. IEEE Symposium on VLSI Technology :194–195

  37. Ye B et al (2021) Suppression of stress-induced defects in FinFET by implantation and STI co-optimization. IEEE Transactions on Electron Devices 68(5):2587–2589. https://doi.org/10.1109/TED.2021.3068241

    Article  CAS  Google Scholar 

  38. Liaw Y-G et al (2016) A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer. Solid State Electron 126:46–50

    Article  CAS  Google Scholar 

  39. Li C, Zhuang Y, Zhang L (2012) Simulation study on FinFET with tri-material gate. IEEE international conference on electron devices and solid state circuit (EDSSC) :1–3

  40. Chang WT et al (2021) Modifying threshold voltages to n- and p- type FinFETs by work function metal stacks. IEEE Open Journal of Nanotechnology:72–77. https://doi.org/10.1109/OJNANO.2021.3109897

  41. Tawfik S. A (2009) FinFET Technology Development Guidelines for Higher Performance , Lower Power , and Stronger Resilience to Parameter Variations. 52nd IEEE International Midwest Symposium on Circuits and Systems :431–434. https://doi.org/10.1109/ICCAD.2005.1560065

  42. King T.-J. (2005) FinFETs for nanoscale CMOS digital integrated circuits. IEEE/ACM International Conference on Computer-Aided Design :207–210

  43. Chang L et al (2002) Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs. IEEE Transactions on Electron Devices 49:2288–2294

    Article  Google Scholar 

  44. Wann C.H, Noda K, Tanaka T, Chenming Hu (1996) A comparative study of advanced MOSFET concepts. IEEE Transactions on Electron Devices 43(10):1742–1753

  45. Lindert N et al (2001) Sub-60-nm quasi-planar FinFETs fabricated using a simplified process IEEE Electron device Lett. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process IEEE Electron Device Letters 22(10):487–489

    CAS  Google Scholar 

  46. Sun, J. et al. (2018) Self-Heating Effects Investigation on Nanoscale FinFET and Its Thermal Resistance Modeling. 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) :1–3

  47. Natarajan S. et al. (2014) A 14nm Logic Technology Featuring 2 nd -Generation FinFET Interconnects, Self-Aligned Double Patterning and a 0 0588 m 2 SRAM cell size. IEEE International Electron Devices Meeting :71–73. https://doi.org/10.1109/ICICDT.2015.7165883

  48. Bardon M. G. et al. (2015) Dimensioning for power and performance under 10nm: The limits of FinFETs scaling 2015 Int Conf IC Des Technol. IEEE International Conference on IC Design & Technology (ICICDT) :10–13

  49. Razavieh A, Zeitzoff P, Nowak EJ (2019) Challenges and limitations of CMOS scaling for FinFET and beyond architectures. IEEE Trans Nanotechnol 18:999–1004

    Article  CAS  Google Scholar 

  50. Ding Y. et al. (2020) A Device Design for 5 nm Logic FinFET Technology. China Semiconductor Technology International Conference(CSTIC) :1–5

  51. De S et al (2021) Robust binary neural network operation from 233 K to 398 K via gate stack and Bias optimization of ferroelectric FinFET synapses. IEEE Electron Device Letters 42(8):1144–1147. https://doi.org/10.1109/LED.2021.3089621

    Article  CAS  Google Scholar 

  52. Saini S., Kashyap M. P., and Chaujar R., (2021) “Recessed channel carbon nanotube truncated fin finfet for high performance ULSI applications,” Proc. 4th Int. Conf. Devices Integr. Circuit, DevIC: 124–128, 2021,. https://doi.org/10.1109/DevIC50843.2021.9455799

  53. Chiang C. K. et al. (2021) “FinFET Plus: A scalable FinFET architecture with 3D air-gap and air-spacer toward the 3nm generation and beyond,” International Symposium on VLSI Technology, Systems and Applications :2–3. https://doi.org/10.1109/VLSITSA51926.2021.9440097

  54. Sehgal HD, Pratap Y, Gupta M, Kabra S (2021) Performance analysis and optimization of under-gate dielectric modulated Junctionless FinFET biosensor. IEEE Sensors J 21(17):18897–18904. https://doi.org/10.1109/JSEN.2021.3090263

    Article  CAS  Google Scholar 

  55. Li Y, Hwang CH, Han MH (2010) Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations. Nanotechnology 21(9)

  56. Kumar US, Rao VR, Member SA (2016) Thermal-aware device design considerations for nanoscale SOI and bulk FinFETs. IEEE Transactions on Electron Devices 63(1):280–287

    Article  CAS  Google Scholar 

  57. Chen HY et al (2011) A novel nanoinjection lithography (NInL) technology and its application for 16-nm node device fabrication. IEEE Transactions on Electron Devices 58(11):3678–3686

    Article  CAS  Google Scholar 

  58. Li Y, Cheng HW (2012) Random work-function-induced threshold voltage fluctuation in metal-gate MOS devices by Monte Carlo simulation. IEEE Trans Semicond Manuf 25(2):266–271

    Article  Google Scholar 

  59. Liao Y. B, Chiang M. H, Lai Y. S, Hsu W. C (2014) Stack gate technique for dopingless bulk FinFETs. IEEE Transactions on Electron Devices 61(4):963–968

  60. Li Y, Hwang CH, Li TY, Han MH (2010) Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies. IEEE Transactions on Electron Devices 57(2):437–447

    Article  CAS  Google Scholar 

  61. Seoane N et al (2014) Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs finFET. IEEE Transactions on Electron Devices 61(2):466–472

    Article  CAS  Google Scholar 

  62. Baravelli E, Jurczak M, Speciale N, De Meyer K, Dixit A (2008) Impact of LER and random dopant fluctuations on FinFET matching performance. IEEE Trans Nanotechnol 7(3):291–298

    Article  Google Scholar 

  63. Li Y, Cheng HW (2012) Statistical device simulation of physical and electrical characteristic fluctuations in 16-nm-gate high-κ/metal gate MOSFETs in the presence of random discrete dopants and random interface traps. Solid State Electron 77:12–19

    Article  CAS  Google Scholar 

  64. Han J. W. et al.(2013) A replacement of high-k process for CMOS transistor by atomic layer deposition. Semiconductor science and technology 28(8):

  65. Brozek T et al (2015) Contact chains for FinFET Technology characterization. IEEE Transactions on Electron Devices 28(3):205–212

    Google Scholar 

  66. Su PH, Li Y (2015) Source/drain series resistance extraction in HKMG multifin bulk FinFET devices. Transactions on Semiconductor Manufacturing 28(2):193–199

    Article  Google Scholar 

  67. Su P.H, Li Y (2016) A systematic approach to correlation analysis of in-line process parameters for process variation effect on electrical characteristic of 16-nm HKMG Bulk FinFET devices. IEEE Transactions on Semiconductor Manufacturing 29(3):209–216. https://doi.org/10.1109/IEDM.2012.6479065

  68. Nainani A. et al. (2012) Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks. IEEE International Electron Devices Meeting :18.3.1–18.3.4. https://doi.org/10.1109/ISTDM.2012.6222469

  69. Choi M, Moroz V, Smith L, Penzin O (2012) 14 nm FinFET stress engineering with epitaxial SiGe source/drain 2012 Int Silicon-Germanium Technol Device Meet. International Silicon-Germanium Technology and Device Meeting (ISTDM) :1–2

  70. Zhao J., Zhao H., and Zhang J. et al. (2021) “Improvement of Fin Bridge Defect for Finfets Technology,” China Semicond. Technol. Int. Conf. CSTIC: 4–7. https://doi.org/10.1109/CSTIC52283.2021.9461555

  71. Auth C. et al.(2012) A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors , Self-Aligned Contacts and High Density MIM Capacitors. IEEE symposium on VLSI technology (VLSIT) :131–132

  72. Choi C, Goo J, Yu Z, Dutton RW (2000) Shallow source/drain extension effects on external resistance in Sub-01 m MOSFET’s. IEEE Transactions on Electron Devices 47(3):655–658

    Article  CAS  Google Scholar 

  73. Jeong J, Yoon JS, Lee S, Baek RH (2020) Comprehensive analysis of source and drain recess depth variations on silicon Nanosheet FETs for sub 5-nm node SoC application. IEEE Access 8:35873–35881

    Article  Google Scholar 

  74. Yakimets D et al (2015) Vertical GAAFETs for the ultimate CMOS scaling. IEEE Transactions on Electron Devices 62(5):1433–1439

    Article  Google Scholar 

  75. Pandey R, Agrawal N, Arghavani R, Datta S (2015) Analysis of Local Interconnect Resistance at Scaled Process Nodes. IEEE 73rd Annual Device Research Conference (DRC) :2014–2015

  76. Choi Y, An J, Yu B (2003) Physical Insights on Design and Modeling of Nanoscale FinFETs. IEEE International Electron Devices Meeting :29.1.1–29.1.4

  77. Koike J, Hosseini M, Ando D, Sutou Y (2018) New Contact Metallization Scheme for FinFET and Beyond 2018. IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) :169–171

  78. N. Loubet et al. (2017) “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET,” IEEE Symposium on VLSI Technology :T230-T231

  79. Mertens H. et al. (2016) Gate-All-Around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. IEEE Symposium on VLSI Technology :1–2 . https://doi.org/10.1109/IEDM.2006.346840

  80. Singh N. et al. (2006) Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. IEEE International Electron Devices Meeting :1–4

  81. Collaert N (2016) Device Architectures for the 5 nm Technology Node and Beyond, [online] Available: http://www.semicontaiwan.org/en/ic-forum-0; https://doi.org/10.1109/essder.2004.1356515

  82. Städele M. et al. (2004) A comprehensive study of corner effects in tri-gate transistors . IEEE Proceedings of the 30th European Solid-State Circuits Conference :165–168

  83. Nagy D, Indalecio G, Garc A. J, Elmessary M. A, Kalna K(2018) FinFET versus gate-all-around nanowire FET : performance , scaling and variability. IEEE Journal of the Electron Devices Society 6:332–340

  84. Thean A.V et al. 3–3 ( Invited ) (2015) Vertical Device Architecture for 5nm and beyond : Device & Circuit Implications. IEEE Symposium on VLSI Technology :T26–T27

  85. Wang R. et al.(2008) Experimental study on quasi-ballistic transport in silicon nanowire transistors and the impact of self-heating effects. IEEE International Electron Devices Meeting :1–4. https://doi.org/10.1109/IEDM.2008.4796806

  86. Cai L, Chen W, Du G, Zhang X, Liu X (2018) Layout design correlated with self-heating effect in stacked Nanosheet transistors. IEEE Transactions on Electron Devices 65(6):2647–2653

    Article  CAS  Google Scholar 

  87. Feng P et al (2017) Comparative analysis of semiconductor device architectures for 5-nm node and beyond. IEEE Electron Device Letters 38(12):1657–1660

    Article  CAS  Google Scholar 

  88. Bufler FM et al (2018) Performance comparison of n-type Si nanowires, Nanosheets, and FinFETs by MC device simulation. IEEE Electron Device Letters 39(11):1628–1631

    Article  CAS  Google Scholar 

  89. Nagy D et al (2020) Benchmarking of FinFET, Nanosheet, and nanowire FET architectures for future Technology nodes. IEEE Access 8:3196–53202

    Article  Google Scholar 

  90. Lee Y. M. et al. (2017) Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology. IEEE International Electron Devices Meeting :29.3.1–29.3.4

  91. Jang D et al (2017) Device exploration of NanoSheet transistors for Sub-7-nm Technology node. IEEE Trans Electron Devices IEEE Transactions on Electron Devices 64(6):2707–2713

    Article  CAS  Google Scholar 

  92. Kim H et al (2020) Optimization of stacked Nanoplate FET for 3-nm node. IEEE Transactions on Electron Devices 67(4):1537–1541

    Article  Google Scholar 

  93. Paul B. C. et al. (2007) Impact of process variation on nanowire and nanotube device performance. IEEE Transactions on Electron Devices 54(9):269–270. https://doi.org/10.1109/IEDM.2008.4796805

  94. Dupré C. et al. (2008) 15nm-diameter 3D stacked nanowires with independent gates operation: φFET. IEEE International Electron Devices Meeting :44287

  95. Xlooruq R.Q.J.L.P. et al. (2015) Performance trade-offs in FinFET and GAA device architecturesfor 7nm-node and beyond. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) :44256

  96. Mohapatra E et al (2021) Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Applied Sciences 3(5):1–13. https://doi.org/10.1007/s42452-021-04539-y

    Article  CAS  Google Scholar 

  97. Neelam A.K, “Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters,” pp. 1–17, 2021. Available online at https://doi.org/10.21203/rs.3.rs-965209/v1

  98. He X. et al. (2017) Impact of Aggressive Fin Width Scaling on FinFET Device Characteristics. IEEE International Electron Devices Meeting :20.2.1–20.2.4

  99. Su PH, Li Y (2018) Analysis of in-line process parameters of the Unity gain frequency of HKMG bulk FinFET devices. IEEE Electron Device Letters 39(3):335–338

    Article  CAS  Google Scholar 

  100. Su PH, Li Y (2016) Process-dependence analysis for characteristic improvement of ring oscillator using 16-nm bulk FinFET devices. IEEE Transactions on Electron Devices 63(8):3058–3063

    CAS  Google Scholar 

  101. Yoon JS, Baek CK, Baek RH (2016) Process-induced variations of 10-nm node bulk nFinFETs considering middle-of-line Parasitics. IEEE Transactions on Electron Devices 63(9):3399–3405

    Article  CAS  Google Scholar 

  102. Xu N, Ho B, Choi M, Moroz V, Liu TJK (2012) Effectiveness of stressors in aggressively scaled FinFETs. IEEE Transactions on Electron Devices 59(6):1592–1598

    Article  CAS  Google Scholar 

  103. Md Rezali FA, Othman NAF, Mazhar HSWM, Soin N (2016) Performance and device design based on geometry and process considerations for 14/16-nm strained FinFETs. IEEE Transactions on Electron Devices 63(9):974–981

    Article  CAS  Google Scholar 

  104. Yakimets D. et al. (2017) Power Aware FinFET and Lateral Nanosheet FET Targeting for 3nm CMOS Technology. IEEE International Electron Devices Meeting :20.4.1–20.4.4

  105. Cai L. et al. (2019) A Physics-based Thermal Model of Nanosheet MOSFETs for Device-Circuit Co-design. IEEE International Electron Devices Meeting :33.6.1–33.6.4

  106. Venkateswarlu S, Badami O, Nayak K (2021) Electro-thermal performance boosting in stacked Si gate-all-around Nanosheet FET with engineered source/drain contacts. IEEE Transactions on Electron Devices 68(9):4723–4728. https://doi.org/10.1109/TED.2021.3095038

    Article  CAS  Google Scholar 

  107. Tayal S. et al. (2021) “A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective,” Silicon:1–8. https://doi.org/10.1007/s12633-021-01128-x

  108. Y. Tian et al. (2007) “New self-aligned silicon nanowire transistors on bulk substrate fabricated by epi-free compatible cmos technology: Process integration, experimental characterization of carrier transport and low frequency noise,” IEEE International Electron Devices Meeting Technical Digest: 895–898. https://doi.org/10.1109/IEDM.2007.4419094

  109. Seoane N et al (2021) Simulations of statistical variability in n-type FinFET, nanowire, and nanosheet FETs. IEEE Electron Device Letters 42(10):1416–1419. https://doi.org/10.1109/LED.2021.3109586

    Article  Google Scholar 

Download references

Acknowledgements

I wish to acknowledge the guidance and valuable feedback provided by Dr. Bulusu Anand (Professor, Electronics and Communication Engineering department, Indian Institute of Technology Roorkee) during the planning and development of this research work.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology Noida, Uttar Pradesh, 201014, India

    Archana Pandey

Authors
  1. Archana Pandey
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Archana Pandey.

Ethics declarations

Conflicts of Interest/Competing Interests

Not applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Pandey, A. Recent Trends in Novel Semiconductor Devices. Silicon 14, 9211–9222 (2022). https://doi.org/10.1007/s12633-022-01694-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-022-01694-8

Keywords

Search

Navigation