Skip to main content
SpringerLink
Log in

Performance Improvement of Dopingless Transistor for Low Power Applications

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

In this paper, we propose the use of metal layer in the oxide region of charge plasma based dopingless transistor for the suppression of band to band tunneling induced leakage current. Using 2-D TCAD simulations, the device behavior of metal layer inserted dopingless transistor (hereafter referred to as ML-DLT) is analyzed and compared with the conventional DLT. We observe that the ML-DLT offers significant improvement in terms of OFF-current reduction by ~5 orders as compared to DLT. The low workfunction metal layer inserted under the drain electrode at the tunneling junction modulates the carrier concentration at the junction, thereby, widening the tunnel barrier at the gate-drain interface in OFF-state. The ON-current is only marginally affected for ML-DLT as metal layer plays a significant role only in the OFF-state. The ION to IOFF ratio is increased by ~5 orders which increases its utility for digital circuits. Gate length scaling demonstrates that, even for LG=5nm, ML-DLT offers better performance in terms of IOFF and ION/IOFF ratio. The ML-DLT shows smaller DIBL and SS values for all gate lengths scaled from LG=20 nm to LG=5 nm. To consider the practical scenario, a misalignment study has also been carried out. Misalignment study reveals that after a misalignment of metal layer towards the channel side by 20nm the device performance is comparable to DLT. We observe that ML-DLT shows superior performance in terms of parameters such as VEA, GM/ID, GM/ID x fT and intrinsic delay τ. Thus, it proves to be a useful technique to suppress the leakage current and enrich the device performance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

There is no other associated data related to manuscript. No data is used for the research described in the manuscript.

References

  1. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229. https://doi.org/10.1038/nnano.2010.15

    Article  CAS  PubMed  Google Scholar 

  2. Sahay S, Kumar MJ (2019) Junctionless field-effect transistors: design, modeling and simulation. Wiley, Hoboken

  3. A. Gnudi, S. Reggiani, E. Gnani, G. Baccarani, Analysis of threshold voltage variability due to random dopant fluctuations in junctionless FETs, IEEE Electron Device Lett. 33 (2012) 336–338. https://doi.org/10.1109/LED.2011.2181153.

    Article  Google Scholar 

  4. P.K. Verma, S.K. Gupta, An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications, Silicon. 13 (2021) 1519–1539. https://doi.org/10.1007/s12633-020-00518-x.

    Article  CAS  Google Scholar 

  5. Chen Z, Xiao Y, Tang M, Xiong Y, Huang J, Li J, Gu X, Zhou Y (2012) Surface-potential-based drain current model for long-channel junctionless double-gate MOSFETs. IEEE Trans Electron Devices 59:3292–3298. https://doi.org/10.1109/TED.2012.2221164

    Article  CAS  Google Scholar 

  6. Sahu C, Singh J (2015) Potential benefits and sensitivity analysis of dopingless transistor for low power applications. IEEE Trans Electron Devices 62:729–735. https://doi.org/10.1109/TED.2015.2389900

    Article  CAS  Google Scholar 

  7. Sahu C, Singh J (2014) Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Lett 35:411–413. https://doi.org/10.1109/LED.2013.2297451

    Article  CAS  Google Scholar 

  8. Gupta G, Rajasekharan B, Hueting RJE (2017) Electrostatic doping in semiconductor devices. IEEE Trans Electron Devices 64:3044–3055. https://doi.org/10.1109/TED.2017.2712761

    Article  CAS  Google Scholar 

  9. Raushan MA, Alam N, Siddiqui MJ (2018) Dopingless tunnel field-effect transistor with oversized back gate: proposal and investigation. IEEE Trans Electron Devices 65:4701–4708. https://doi.org/10.1109/TED.2018.2861943

    Article  CAS  Google Scholar 

  10. Kim M, Kim Y, Lim D, Woo S, Im K, Cho J, Kang H, Kim S (2017) Superlattices and microstructures impact ionization and tunneling operations in charge-plasma dopingless device. Superlattices Microstruct :1–10. https://doi.org/10.1016/j.spmi.2017.07.041

  11. Shan C, Wang Y, Bao MT, Charge-Plasma-Based A (2016) Transistor with induced graded channel for enhanced analog performance. IEEE Trans Electron Devices 63:2275–2281. https://doi.org/10.1109/TED.2016.2549554

    Article  CAS  Google Scholar 

  12. Hur J, Moon D, Han J, Kim G, Jeon C, Choi Y (2017) Tunneling effects in a charge-plasma dopingless transistor. 16: 315–320. https://doi.org/10.1109/TNANO.2017.2663659

  13. Hueting RJE, Rajasekharan B, Salm C, Schmitz J (2008) The charge plasma P-N diode. IEEE Electron Device Lett 29:1367–1369. https://doi.org/10.1109/LED.2008.2006864

    Article  Google Scholar 

  14. Gundapaneni S, Bajaj M, Pandey RK, Murali KVRM, Ganguly S, Kottantharayil A (2012) Effect of band-to-band tunneling on junctionless transistors. IEEE Trans Electron Devices 59:1023–1029. https://doi.org/10.1109/TED.2012.2185800

    Article  CAS  Google Scholar 

  15. Ramaswamy S, Kumar MJ (2016) Raised source/drain dopingless junctionless accumulation Mode FET: design and analysis. IEEE Trans Electron Devices 63:4185–4190. https://doi.org/10.1109/TED.2016.2612263

    Article  CAS  Google Scholar 

  16. Rai MK, Gupta A, Rai S (2021) Comparative analysis & study of various leakage reduction techniques for short channel devices in junctionless transistors: a review and perspective. Silicon. https://doi.org/10.1007/s12633-021-01181-6

  17. Kumar S, Chatterjee AK, Pandey R (2021) Performance analysis of gate electrode work function variations in double-gate junctionless FET. Silicon 13:3447–3459. https://doi.org/10.1007/s12633-020-00774-x

    Article  CAS  Google Scholar 

  18. Raad BR, Tirkey S, Sharma D, Kondekar P (2017) A new design approach of dopingless tunnel FET for enhancement of device characteristics. IEEE Trans Electron Devices 64:1830–1836. https://doi.org/10.1109/TED.2017.2672640

    Article  CAS  Google Scholar 

  19. Tirkey S, Sharma D, Yadav DS, Yadav S (2017) Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters. IEEE Trans Electron Devices 64:3943–3950. https://doi.org/10.1109/TED.2017.2730922

    Article  CAS  Google Scholar 

  20. Kim K, Lee HBR, Johnson RW, Tanskanen JT, Liu N, Kim MG, Pang C, Ahn C, Bent SF, Bao Z (2014) Selective metal deposition at graphene line defects by atomic layer deposition. Nat Commun 5. https://doi.org/10.1038/ncomms5781

  21. Törndahl T, Ottosson M, Carlsson JO (2004) Growth of copper metal by atomic layer deposition using copper(I) chloride, water and hydrogen as precursors. Thin Solid Films 458:129–136. https://doi.org/10.1016/j.tsf.2003.12.063

    Article  CAS  Google Scholar 

  22. Griffiths MBE, Pallister PJ, Mandia DJ, Barry ST (2016) Atomic layer deposition of gold metal. Chem Mater 28:44–46. https://doi.org/10.1021/acs.chemmater.5b04562

    Article  CAS  Google Scholar 

  23. Johnson RW, Hultqvist A, Bent SF (2014) A brief review of atomic layer deposition: From fundamentals to applications. Mater Today 17:236–246. https://doi.org/10.1016/j.mattod.2014.04.026

    Article  CAS  Google Scholar 

  24. Silvaco Int. ATLAS user’s manual a 2D-3D numerical device simulator. Available at http://www.silvaco.com

  25. Hänsch W, Vogelsang T, Kircher R, Orlowski M (1989) Carrier transport near the Si/SiO2 interface of a MOSFET. Solid State Electron 32:839–849. https://doi.org/10.1016/0038-1101(89)90060-9

    Article  Google Scholar 

  26. Baruah RK, Paily RP (2014) A dual-material gate junctionless transistor with high-$k$ spacer for enhanced analog performance. IEEE Trans Electron Devices 61(1):123128. https://doi.org/10.1109/TED.2013.2292852

  27. Strangio S, Settino F, Palestri P, Lanuzza M, Crupi F, Esseni D, Selmi L (2018) Digital and analog TFET circuits: Design and benchmark. Solid State Electron 146:50–65. https://doi.org/10.1016/j.sse.2018.05.003

    Article  CAS  Google Scholar 

Download references

Acknowledgments

This work was carried out under the project of “Visvesvaraya PhD Scheme for Electronics and IT” at Aligarh Muslim University, by Media Lab Asia (A Sect. 25 Company of Department of Electronics and Information Technology, Ministry of Communications and Information Technology, Govt. of India). The revised Implementation Order No is ‘PhD-MLA/4(39)/2015-16/ Dated 30.05·2016’. The authors are also thankful to the UGC of India for DSA-I grant and Start-Up grant.

Funding

“Visvesvaraya PhD Scheme for Electronics and IT” at Aligarh Muslim University, by Media Lab Asia (A Sect. 25 Company of Department of Electronics and Information Technology, Ministry of Communications and Information Technology, Govt. of India).

Author information

Authors and Affiliations

  1. Electronics Engineering Department, ZHCET, Aligarh Muslim University, Aligarh, 202002, India

    Mohd Adil Raushan, MD. Yasir Bashir, Naushad Alam & Mohd Jawaid Siddiqui

Authors
  1. Mohd Adil Raushan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. MD. Yasir Bashir
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Naushad Alam
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Mohd Jawaid Siddiqui
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All the authors have equally contributed in the manuscript.

Corresponding author

Correspondence to MD. Yasir Bashir.

Ethics declarations

This article does not contain any studies involving animals or human participants performed by any of the authors.

Conflict of Interest

The authors declare that they have no conflicts of interest.

Consent to Participate

Not Applicable.

Consent for Publication

Not Applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Raushan, M.A., Bashir, M.Y., Alam, N. et al. Performance Improvement of Dopingless Transistor for Low Power Applications. Silicon 14, 8009–8020 (2022). https://doi.org/10.1007/s12633-021-01556-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-021-01556-9

Keywords

Search

Navigation