Abstract
In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stack-graded channel double gate-Junctionless (TMGS-GCDG-JL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generation-factor (TGF), early voltage, voltage gain, unity-power-gain frequency (fmax), unity-current-gain frequency (ft), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDG-JL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gate-junctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDG-JL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.
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The data that support the findings of this study are available from the corresponding author, upon reasonable request.
References
Thompson SE, Armstrong M, Auth C, Cea S, Chau R, Glass G, Hoffman T, Klaus J, Ma Z, Mcintyre B, Murthy A, Obradovic B, Shifren L, Sivakumar S, Tyagi S, Ghani T, Mistry K, Bohr M, El-Mansy Y (2004) A logic nanotechnology featuring strained-silicon. IEEE Electron Device Lett 25(4):191–193
Jurczak M, Skotnicki T, Ricci G, Campidelli Y, Hernandez C, Bensahel D (1999) Study on Enhanced performance in NMOSFETs on strained silicon. In: 29th European solid-state device research conference, vol 1, pp 304–307
Sanuki T, Oishi A, Morimasa Y, Aota S, Kinoshita T, Hasumi R, Takegawa Y, Isobe K, Yoshimura H, Iwai M, Sunouchi K, Noguchi T (2003) Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology. In: IEEE International electron devices meeting 2003, pp 3.5.1–3.5.4
Keith S, Bufler FM, Meinerzhagen B (1997) Full band monte-carlo device simulation of an 0.1 um N-Channel MOSFET in strained silicon material. In: 27th European solid-state device research conference, pp 200–203
Nguyen C, Pham A, Jungemann C, Meinerzhagen B (2005) Study of charge carrier quantization in strained Si-nMOSFETs. Mater Sci Semicond Process 8(1):363–366
Ko CH, Ge CH, Huang CC, Fu CY, Hsu CP, Chen CH, Chang CH, Lu JC, Yeo YC, Lee WC, Chi MH (2005) A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications. In: IEEE VLSI-TSA international symposium on VLSI technology, 2005. (VLSI-TSA-Tech), pp 25–26
Langdo T, Currie MT, Lochtefeld A, Hammond R, Carlin J, Erdtmann M, Braithwaite G, Yang VK, Vineis C, Badawi H, Bulsara M (2003) SiGe-free strained Si on insulator by wafer bonding and layer transfer. Appl Phys Lett 06:4256–4258
Suddapalli SR, Nistala BR (2020) Analytical modeling of subthreshold current and swing of strained-Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance. In: International journal of numerical modelling: Electronic networks, devices and fields
Shankar R, Kaushal G, Maheshwaram S, Dasgupta S, Manhas SK (2014) A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers. IEEE Trans Device Mater Reliab 14(2):689–697
Duksh YS, Singh B, Gola D, Tiwari PK, Jit S (2021) Subthreshold modeling of graded channel double gate junctionless FETs. Silicon 13:1231–1238
Haque MM, Kabir MH, RahmanAdnan MM (2020) Analytical modelling and verification of potential profile of DG JLFET with and without stack oxide. Int J Electron 1–22
Vadthiya N, Girdhardas KA (2018) Surface potential modeling of graded-channel gate-stack (GCGS) high-K dielectric dual-material double-gate (DMDG) MOSFET and analog/RF performance study. Silicon 10:2865–2875
Dubey S, Santra A, Saramekala G, Kumar M, Tiwari PK (2013) An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs. IEEE Trans Nanotechnol 12(5):766–774
Baruah RK, Paily RP (2014) A dual-material gate junctionless transistor with high- k spacer for enhanced analog performance. IEEE Trans Electron Devices 61(1):123–128
Pradhan KP, Mohapatra SK, Sahu PK, Behera DK (2014) Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectron J 45(2):144–151
Baidya A, Baishya S, Lenka T (2017) Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor. Mater Sci Semicond Process 71:413–420
Ferhati H, Djeffal F (2018) Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications. J Comput Electron 17:129–137
Suddapalli SR, Nistala BR (2019) A center-potential-based threshold voltage model for a graded-channel dual-material double-gate strained-Si MOSFET with interface charges. J Comput Electron 18 (4):1173–1181
Ghosh D, Parihar MS, Armstrong GA, Kranti A (2012) High-performance junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Lett 33(10):1477–1479
Chen Y, Mohamed M, Jo M, Ravaioli U, Xu R (2013) Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications. J Comput Electron 12(4):757–764
Singh SA, TripathiComparative S (2019) Analysis of double gate junction less and gate stacked double gate junction less MOSFETs. Semiconductors 53(13):1804–1810
Baral K, Singh PK, Kumar S, Singh A, Tripathy M, Chander S, Jit S (2020) 2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET. AEU - Int J Electron Commun 116:153071
Xiang Q, Goo J-S, Pan J, Yu B, Ahmed S, Zhang J, Lin M-R (2003) Strained silicon NMOS with nickel-silicide metal gate. In: 2003 Symposium on VLSI technology. digest of technical papers (IEEE Cat. No.03CH37407), pp 101–102
Lim J-S, Thompson SE, Fossum JG (2004) Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs. IEEE Electron Device Lett 25(11):731–733
Zhang W, Fossum JG (2005) On the threshold voltage of strained-Si-Si1-xGex MOSFETs. IEEE Trans Electron Devices 52:263–268
Kumar MJ, Venkataraman V, Nawal S (2006) A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs. IEEE Trans Electron Devices 53 (10):2500–2506
Sentaurus Device User Guide (2019) Synopsys, Inc., Mountain View, CA, USA
Omura Y, Horiguchi S, Tabe M, Kishi K (1993) Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs. IEEE Electron Device Lett 14(12):569–571
Suddapalli SR, Nistala BR (2020) The analog/RF performance of a strained-Si graded-channel dual-material double-gate MOSFET with interface charges. J Comput Electron
Acknowledgements
The authors gratefully acknowledge the simulation facilities provided by Analog IC lab, NIT Warangal.
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The authors declare that Suddapalli Subba Rao has received research support from National Institute of Technology Warangal. Further, authors have no other relevant funding or financial support to disclose in relevance to the work shown in this paper.
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All the authors contributed to study conception and conceptualization. Material setup and TCAD simulation are performed by Suddapalli Subba Rao. Formal analysis and investigation of the simulated results were done by Rani Deepika Balavendran Joseph. The first draft of the manuscript was written by D. Srikar and Vijaya Durga Chintala and edited by Suddapalli Subba Rao and Gopi Krishna Saramekala. Finally, the complete work was carried under the supervision of Nistala Bheema Rao.
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Rao, S.S., Joseph, R.D.B., Chintala, V.D. et al. Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges. Silicon 14, 7363–7376 (2022). https://doi.org/10.1007/s12633-021-01462-0
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DOI: https://doi.org/10.1007/s12633-021-01462-0