Abstract
Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices and architecture such as FinFET devices instead of MOSFET. FinFET emerged as a non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering and threshold voltage roll-off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work the reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductors) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7 nm BSIM-CMG Predictive technology model files (PTM) in mentor graphics tool. The FinFET based SRAM showed low leakage, low power dissipation, and less delay compared to existing conventional MOSFET based SRAM.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Data Availability
Not applicable.
References
Sahay S, Kumar MJ (2019) Junctionless Field-effect transistors: design, modeling and simulation, Wiley, Hoboken
Narendar V, Tripathi S, Naik RBS (2018) A two dimensional(2D) analytical modeling and improved short channel performance of Graded-Channel gate-stack(GCGS) dual-material double-gate(DMDG) MOSFET. Silicon 10(6):2399–2407
Nowak EJ, Aller I, Ludwig T, Keunwoo Kim, Joshi RV, Ching-te Chaung, Berstein K, Puri R (2004) Turning silicon on its edge double gate CMOS/FinFET technology, IEEE Circ Devices Mag 20(1):20–31
Sachid AB, Chen M, Hu C (2017) Bulk FinFET with low-k spacers for continued scaling. IEEE Trans Electron Devices 64(4):1861–1864
Sreenivasulu VB, Narendar V (2021) Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications. ECS J. Solid State Sci. Technol 10:013008. https://doi.org/10.1149/2162-8777/abddd4
Yu E, Heo K, Cho S (2018) Characterization and optimization of inverted-T FinFET under nanoscale dimensions. IEEE Trans Electron Dev 65:3521
Jain G, Sawhney RS, Kumar R (2021) Design and investigation of triple metal gate engineering of charge plasma based TFET for biomolecule detection. Mater Today Proc:2214–7853. https://doi.org/10.1016/j.matpr.2021.05.630
Moparthi S, Adarsh KP, Tiwari PK, Saramekala GK (2020) Analog and RF performance evaluation of negative capacitance SOI junctionless transistor. AEU Int J Electron Commun 122:153243. https://doi.org/10.1016/j.aeue.2020.153243
Narendar V, et.al. Investigation of short channel Effects(SCEs) and Analog/RF Figure of merits(FOMs) of dual Material bottom – Spacer Ground -Plane(DMBSGP]. FinFET 2019;12:2283–91
. Tamersit k.Sub – 10nm junctionless carbon nanotube field – effect transistors with improved performance.AEU – Int J Electron Commun 2020;124:153354. 10.1016/j.aeue.2020.153354
Jain G, Sawhney RS, Kumar R, Wadhwa G (2021) Analytical modeling analysis and simulation study of dual material gate underlap dopingless TFET. Superlattices and Microstructures 153:106866
Colinge J-P, Lee C-W, Afzalian A, Akhavan ND, Yan R, Ferain I et al (2010) Nanowire Transistors without Junctions. Nat Nanotechnol 5(3):225–229
Vadthiya N, Narware P, Bheemudu V, Sunitha B (2020) A novel bottom-spacer ground – plane(BSGP) FinFET for improved logic and analog/RF performance. AEU Intl J Electron Commun 127:153459
Sreenivasulu VB, Narendar V (2021) Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length. AEU - Intl J Electron Commun 137:153803. https://doi.org/10.1016/j.aeue.2021.153803
Sreenivasulu VB, Narendar V (2021) Design insights into RF/analog and linearity/distortion of spacer engineered multi-fin SOI FET for terahertz applications. Intl J RF Micro Comput Aided Eng 31(9). https://doi.org/10.1002/mmce.22875
Sreenivasulu VB, Narendar V (2021) A comprehensive analysis of Junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length. Silicon. https://doi.org/10.1007/s12633-021-00987-8
Sreenivasulu VB, Narendar V (2021) Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications. Silicon. https://doi.org/10.1007/s12633-021-01145-w
Dhanumjayal, M. Sudha, M.N. GiriPrasad, K. Padmaraju “Cell stability analysis of conventional 6T dynamic 8T SRAM cell in 45nm technology”, international journal of VLSI design and communication systems(VLSICs) Vol. 3, No. 2, April 2012
J. Sallese, N. Chevillon, C. Lallement, B. Iniguez, and F. Pregaldiny,“Charge based modelling of Junctionless double gate Field Effect Transsistors”,IEEE Trans Electronic devices,58,2628(2011)
A. Carlson, Z. Guo, S. Balasubramanian, R. Zlatanovici, T. K. Liu, B. Nikolic, SRAM Read/Write margin enhancements using FinFETs, IEEE trans very large scale Integr, Syst.18(6) (2010) 887–900
L. Baghriye, S. Toofan, R. Saeidi, F. Moradi, offset-Compensated high Speed Sense Amplifier for STT – MRAMs, IEEE Trans Very Large Scale Integr, (2018), 1051–1058
Panigrahy AK, Ghosh T, Vanjari SRK, Singh SG (2019) Surface density gradient engineering precedes enhanced diffusion; drives CMOS in-line process flow compatible cu–cu thermocompression bonding at 75° C. IEEE Trans Device Mater Reliab 19(4):791–795
A.K. Panigrahy, S. Bonam, T. Ghosh, S.R.K. Vanjari, and S.G. Singh, 2019. Diffusion enhanced drive sub 100 C wafer level fine-pitch cu-cu thermocompression bonding for 3D IC integration. In 2019 IEEE 69th electronic components and technology conference (ECTC) (pp. 2156-2161). IEEE
Panigrahi AK, Bonam S, Ghosh T, Singh SG, Vanjari SRK (2016) Ultra-thin Ti passivation mediated breakthrough in high quality cu-cu bonding at low temperature and pressure. Mater Lett 169:269–272
Acknowledgements
The authors are thankful to the Kakatiya University and Mahatma Gandhi Institute of technology for their cooperation and support during this research work.
Funding
No funding received to carry out this research work.
Author information
Authors and Affiliations
Contributions
A. Navaneetha: Data Collection, Formal analysis,Simulation,original draft preparation, Dr. K. Bikshalu: Supervision, Conceptualization, methodology.
Corresponding author
Ethics declarations
Consent to Participate
Yes
Consent for Publication
Yes
Conflict of Interest
The authors declare that they have no known competing interest or personal relationship that could have appeared to influence the work reported in this paper.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Navaneetha, A., Bikshalu, K. Reliability and Power Analysis of FinFET Based SRAM. Silicon 14, 5855–5862 (2022). https://doi.org/10.1007/s12633-021-01345-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-021-01345-4