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GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security

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Abstract

Intellectual property (IP) security has emerged as a critical concern in semiconductor industries. In the domain of hardware IP security, logic locking is a commonly used technique to prevent unauthorized access to IPs. This article proposes a conceptual pipeline to enhance the hardware IP security by leveraging generative models and logic locking concepts (GAN4IP) for hardware IP security. The proposed approach uses the concept of logic locking and generative adversarial networks (GANs) in a unified fashion to design secure hardware IPs. The GAN architecture uses deep learning techniques and graph-based representations of digital circuits to build obfuscated designs that can predict the behavior of locked netlists and generate secure designs. The proposed perspective method opens up new avenues for further investigation of highly secure electronic system design and has the potential to significantly impact the field of hardware IP security.

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Acknowledgements

Jugal Gandhi acknowledges the fellowship support provided by CSIR-Human Resource Development Group (HRDG).

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Authors and Affiliations

  1. CSIR - Central Electronics Engineering Research Institute, Pilani, 333031, India

    Jugal Gandhi, Diksha Shekhawat, M Santosh & Jai Gopal Pandey

  2. Academy of Scientific and Innovative Research (AcSIR), Ghaziabad, 201002, India

    Jugal Gandhi, Diksha Shekhawat, M Santosh & Jai Gopal Pandey

Authors
  1. Jugal Gandhi
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  2. Diksha Shekhawat
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  3. M Santosh
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  4. Jai Gopal Pandey
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Corresponding author

Correspondence to Jai Gopal Pandey.

Appendix

Appendix

The GitHub repository will be regularly updated, ensuring the inclusion of the recent code, datasets, and relevant research materials. The project is actively managed with periodic updates to reflect ongoing work. The latest version is available at https://github.com/Sky025/GAN4IP.git.

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Gandhi, J., Shekhawat, D., Santosh, M. et al. GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security. Sādhanā 49, 169 (2024). https://doi.org/10.1007/s12046-024-02461-8

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