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Summarization of Boolean satisfiability verification

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Journal of Electronics (China)

Abstract

As a complementary technology to Binary Decision Diagram-based (BDD-based) symbolic model checking, the verification techniques on Boolean satisfiability problem have gained an increasing wide of applications over the last few decades, which brings a dramatic improvement for automatic verification. In this paper, we firstly introduce the theory about the Boolean satisfiability verification, including the description on the problem of Boolean satisfiability verification, Davis-Putnam-Logemann-Loveland (DPLL) based complete verification algorithm, and all kinds of solvers generated and the logic languages used by those solvers. Moreover, we formulate a large number optimizations of technique revolutions based on Boolean SATisfiability (SAT) and Satisfiability Modulo Theories (SMT) solving in detail, including incomplete methods such as bounded model checking, and other methods for concurrent programs model checking. Finally, we point out the major challenge pervasively in industrial practice and prospect directions for future research in the field of formal verification.

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References

  1. E. M. Clarke, O. Grumberg, and D. A. Peled. Model Checking. Cambridge, Massachusetts, London, England, MIT Press, 1999, 35–95.

    Google Scholar 

  2. K. L. McMillan. Class project on BDD-based verification. Private Communication, EM Clarke, 1987.

    Google Scholar 

  3. A. Biere, A. Cimatti, E. M. Clarke, et al.. Symbolic model checking using SAT procedures instead of BDDs. Proceedings of the 36th Annual IEEE/ACM Design Automation Conference, New Orleans, LA, USA, June 1999, 317–320.

  4. A. Biere, A. Cimatti, E. M. Clarke, et al.. Symbolic model checking without BDDs. Proceedings of the 5th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Amsterdam, the Netherlands, March 1999, 193–207.

  5. K. L. McMillan. Applying SAT methods in un bounded symbolic model checking. Computer Aided Verification, Copenhagen, Denmark, July 2002, 250–264.

  6. A. Armando, J. Mantovani, and L. Platania. Bounded model checking of software using SMT solvers instead of SAT solvers. International Journal on Software Tools for Technology Transfer, 11(2009)1, 69–83.

    Article  Google Scholar 

  7. B. Selman, H. A. Kautz, and B. Cohen. Noise strategies for improving local search. Proceedings of the 12th National Conference on Artificial Intelligence, Seattle, WA, USA, July 1994, 337–343.

  8. B. Selman, H. J. Levesque, and D. Mitchell. A new method for solving hard satisfiability problems. Proceedings of the 10th National Conference on Artificial Intelligence, San Jose, CA, USA, July 1992, 440–446.

  9. J. P. Marques-Silva and K. A. Sakallah. GRASP: a search algorithm for propositional satisfiability. IEEE Transactions on Computers, 48(1999)5, 506–521.

    Article  MathSciNet  Google Scholar 

  10. H. Zhang. SATO: an efficient prepositional prover. Conference on automated Deduction, Townsville, Nor-th Queensland, Australia, July 1997, 272–275.

  11. M. W. Moskewicz, C. F. Madigan, Y. Zhao, et al.. Chaff: engineering an efficient SAT solver. Proceedings of the 38th Annual Design Automation Conference, Las Vegas, NV, USA, June 2001, 530–535.

  12. L. Zhang and S. Malik. The quest for efficient Boolean satisfiability solvers. Computer Aided Verification, Copenhagen, Denmark, July 2002, 17–36.

  13. B. Dutertre and L. De Moura. The yices SMT solver. Tool paper at http://yices.csl.sri.com/tool-paper.pdf, 2006, 2: 2.

    Google Scholar 

  14. L. De Moura and N. Bjørner. Z3: an efficient SMT solver. Tools and Algorithms for the Construction and Analysis of Systems, Budapest, Hungary, March 2008, 337–340.

  15. F. Maric and P. Janicic. Argo-LIB v3. 5: system description for smtcomp’07. Technical Report, Matematicki Fakultet Univerziteta u Beogradu, 2007.

    Google Scholar 

  16. L. De Moura and N. Bjørner. Satisfiability modulo theories: introduction and applications. Communications of the ACM, 54(2011)9, 69–77.

    Article  Google Scholar 

  17. N. Shankar and M. Vaucher. The mechanical verification of a DPLL-based satisfiability solver. Electronic Notes in Theoretical Computer Science, 269 (2011), 3–17.

    Article  MathSciNet  Google Scholar 

  18. N. Eén and A. Biere. Effective preprocessing in SAT through variable and clause elimination. Theory and Applications of Satisfiability Testing, St. Andrews, Scotland, UK, June 2005, 61–75.

  19. L. Zhang. On subsumption removal and on-the-fly CNF simplification. Theory and Applications of Satisfiability Testing, St. Andrews, Scotland, UK, June 2005, 482–489.

  20. J. Marques-silva. The impact of branching heuristics in propositional satisfiability algorithms. Proceedings of the 9th Portuguese Conference on Artificial Intelligence, Évora, Portugal, September 1999, 62–74.

  21. C. Wang, H. S. Jin, G. D. Hachtel, et al.. Refining the SAT decision ordering for bounded model checking. Proceedings of the 41st Annual Design Automation Conference, San Diego, CA, USA, June 2004, 535–538.

  22. M. Davis, G. Logemann, and D. Loveland. A machine program for theorem-proving. Communications of the ACM, 5(1962)7, 394–397.

    Article  MATH  MathSciNet  Google Scholar 

  23. M. Davis and H. Putnam. A computing procedure for quantification theory. Journal of the ACM, 7(1960)3, 201–215.

    Article  MATH  MathSciNet  Google Scholar 

  24. A. Van Gelder. Generalized conflict-clause strengthening for satisfiability solvers. Theory and Applications of Satisfiability Testing, Ann Arbor, MI, USA, June 2011, 329–342.

  25. A. Gupta, M. Ganai, Z. Yang, et al.. Iterative abstraction using SAT-based BMC with proof analysis. International Conference on Computer-Aided Design, San Jose, CA, USA, November 2003, 416–423.

  26. O. Strichman. Pruning techniques for the SAT-based bounded model checking problem. Proceedings of the 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Livingston, Scotland, UK, Septembe 2001, 58–70.

  27. A. Gupta, M. Ganai, C. Wang, et al.. Learning from BDDs in SAT-based bounded model checking. Proceedings of Design Automation Conference, Anaheim, CA, USA, June 2003, 824–829.

  28. P. F. Williams, A. Biere, E. M. Clarke, et al.. Combining decision diagrams and SAT procedures for efficient symbolic model checking. Proceedings of the 12th International Conference on Computer Aided Verification, Chicago, IL, USA, July 2000, 124–138.

  29. A. Gupta, Z. Yang, P. Ashar, and A. Gupta. SAT-based image computation with application in reachability analysis. Proceedings of the 3rd International Conference on Formal Methods in Computer-Aided Design, Austin, TX, USA, Novembe 2000, 354–371.

  30. G. Cabodi, S. Nocco, and S. Quer. Improving SAT-based bounded model checking by means of BDD-based approximate traversals. Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany, March 2003, 10898–10905.

  31. S. G. Govindaraju and D. L. Dill. Verification by approximate forward and backward reachability. Computer-Aided Design, San Jose, CA, USA, 1998, 366–370.

    Google Scholar 

  32. A. Armando, M. Benerecetti, and J. Mantovani. Counterexample-guided abstraction refinement for linear programs with arrays. Proceedings of the 28th IEEE/ACM International Conference on Automated Software Engineering, Crowne Plaza Cabana, Palo Alto, CA, USA, Novembe 2013, 1–61.

  33. E. M. Clarke, O. Grumberg, S. Jha, et al.. Counterexample-guided abstraction refinement for symbolic model checking. Journal of the ACM, 50(2003)5, 752–794.

    Article  MathSciNet  Google Scholar 

  34. C. Wang, B. Li, H. S. Jin, et al.. Improving ariadne’s bundle by following multiple threads in abstraction refinement. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 25(2006)11, 2297–2316.

    Article  Google Scholar 

  35. K. L. McMillan and N. Amla. Automatic abstraction without counterexamples. Tools and Algorithms for the Construction and Analysis of Systems, Warsaw, Poland, April 2003, 2–17.

  36. J. Marques-Sila and J. Planes. Algorithms for maximum satisfiability using unsatisfiable cores. Advanced Techniques in Logic Synthesis, Optimizations and Applications, NY, USA, Springer New York, 2011, 171–182.

    Chapter  Google Scholar 

  37. L. Zhang and S. Malik. Extracting small unsatisfiable cores from unsatisfiable Boolean formula. Theory and Applications of Satisfiability Testing, Santa Margherita Ligure, Italy, May 2003, 287–298.

  38. Y. Oh, M. N. Mneimneh, Z. S. Andraus, et al.. AMUSE: a minimally-unsatisfiable subformula extractor. Proceedings of the 41st annual Design Automation Conference, San Diego, CA, USA, June 2004, 518–523.

  39. I. Lynce and J. P. Marques-Silva. On computing minimum unsatisfiable cores. Proceedings of the 7th International Conference on Theory and Applications of Satisfiability Testing. Vancouver, BC, Canada, May 2004, 305–310.

  40. L. Cordeiro, B. Fischer, and J. Marques-Silva. SMT-based bounded model checking for embedded ANSI-C software. Software Engineering, 38(2012)4, 957–974.

    Article  Google Scholar 

  41. T. Liu, M. Nagel, and M. Taghdiri. Bounded program verification using an smt solver: a case study. 2012 IEEE 5th International Conference on Software Testing, Verification and Validation, Montreal, QC, Canada, April 2012, 101–110.

  42. M. Junker, R. Huuck, A. Fehnker, et al.. SMT-based false positive elimination in static program analysis. Formal Methods and Software Engineering, Kyoto, Japan, November 2012, 316–331.

  43. D. Kroening. Automated verification of concurrent software. Reachability Problems, Uppsala, Sweden, September 2013, 19–20.

  44. A. Lal, S. Qadeer, and S. K. Lahiri. A solver for reachability modulo theories. Computer Aided Verification, Berkeley, CA, USA, July 2012, 427–443.

  45. S. Qadeer and J. Rehof. Context-bounded model checking of concurrent software. Proceedings of the 11st International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Edinburgh, UK, April 2005, 93–107.

  46. L. Cordeiro and B. Fischer. Verifying multi-threaded software using smt-based context-bounded model checking. Proceedings of the 33rd International Conference on Software Engineering, Honolulu, HI, USA, May 2011, 331–340.

  47. O. Grumberg, F. Lerda, O. Strichman, et al.. Proof-guided underapproximation-widening for multi-process systems. Proceedings of the 32nd International Conference on Principles of Programming Languages, Long Beach, CA, USA, January 2005, 122–131.

  48. C. Wang, S. Chaudhuri, A. Gupta, et al.. Symbolic pruning of concurrent program executions. Proceedings of the 7th Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering, Amsterdam, the Netherlands, August 2009, 23–32.

  49. C. Wang, S. Kundu, R. Limaye, et al.. Symbolic predictive analysis for concurrent programs. Formal Aspects of Computing, 23(2011)6, 781–805.

    Article  MATH  MathSciNet  Google Scholar 

  50. I. Dillig, T. Dillig, K. L. McMillan, et al.. Minimum satisfying assignments for SMT. Computer Aided Verification, Berkeley, CA, USA, July 2012, 394–409.

  51. A. Stump, D. Oe, A. Reynolds, et al.. SMT proof checking using a logical framework. Formal Methods in System Design, 42(2013)1, 91–118.

    Article  MATH  Google Scholar 

  52. D. R. Cok, A. Griggio, and R. Bruttomesso. The 2012 SMT Competition. Tool paper at http://smt2012.loria.fr/SMT-COMP2012.pdf.

  53. A. Cimatti, A. Griggio, and R. Sebastiani. A simple and flexible way of computing small unsatisfiable cores in SAT modulo theories. Theory and Applications of Satisfiability Testing, Lisbon, Portugal, May 2007, 334–339.

  54. A. Cimatti, A. Griggio, and R. Sebastiani. Computing small unsatisfiable cores in satisfiability modulo theories. Journal of Artificial Intelligence Research, 40(2011)1, 701–728.

    MATH  MathSciNet  Google Scholar 

  55. J. Zhang, W. Xu, J. Zhang, et al.. Finding first-order minimal unsatisfiable cores with a heuristic depth-first-search algorithm. Intelligent Data Engineering and Automated Learning, Norwich, UK, September 2011, 178–185.

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Authors and Affiliations

  1. Guangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, 541004, China

    Junyan Qian, Juan Wu, Lingzhong Zhao & Yunchuan Guo

Authors
  1. Junyan Qian
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  2. Juan Wu
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  3. Lingzhong Zhao
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  4. Yunchuan Guo
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Corresponding author

Correspondence to Junyan Qian.

Additional information

Supported by the National Natural Science Foundation of China (Nos. 61063002, 61100186, 61262008), Guangxi Natural Science Foundation of China (2011GXNSFA-018164, 2011GXNSFA018166, 2012GXNSFAA053220), and the Key Project of Education Department of Guangxi.

Qian Junyan, born in 1973, male, Ph.D. and Professor.

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Qian, J., Wu, J., Zhao, L. et al. Summarization of Boolean satisfiability verification. J. Electron.(China) 31, 232–245 (2014). https://doi.org/10.1007/s11767-014-3158-y

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  • DOI: https://doi.org/10.1007/s11767-014-3158-y

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