Abstract
This paper proposes an architecture consisting of various edge detection filters implemented on modern FPGA platforms exploiting a feature of dynamic partial reconfiguration (DPR). The developed system targets small-scale systems, and its use in the educational setting can be of great interest. Two-dimensional convolution is the most common operation in digital video/image processing, and its implementation is highly demanding in terms of computational intensity, high throughput and hardware resources. In the case of a variety of filtering techniques used for edge detection, the hardware resources become a constraint, in particular when using convolution kernels with varying parameters and sizes. DPR introduces significant functional density and increased flexibility by providing logic switching within a constrained hardware area. Furthermore, parallel and pipelined hardware solutions for filter implementation overcome computational performance of software solutions and increase effectiveness compared to static hardware solution. The advantages of accommodating a number of various algorithms within the same datapath at low cost and considerable time are exploited in the proposed work. The effectiveness of the DPR feature for edge detection application is tested on the filter scenarios varying in sizes, complexity and intensity of computation, where the resource utilization and timing are evaluated. Experimental results are proposed through comparisons between different configurations (with DPR and without DPR) and detailed performance analysis.
Similar content being viewed by others
References
Liu, J., Wang, S., Li, Y., Han, J., Zeng, X.Y.: Configurable pipelined Gabor filter implementation for fingerprint image enhancement. In: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), IEEE, pp. 584–586 (2010)
Wang, X.X., Shi, B.E.: GPU implementation of fast Gabor filters. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 373–376 (2010)
Iandola, F.N., Sheffield, D., Anderson, M.J., Phothilimthana, P.M., Keutzer, K.: (2013) Communication-minimizing 2D convolution in GPU registers. In: 2013 20th IEEE International Conference on Image Processing (ICIP), pp. 2116–2120
Lourenzo L.H.A., Weingaertner, D., Todt, E.: Efficient Implementation of Canny edge detection filter for ITK using CUDA. In: 2012 13th Symposium on Computer Systems (WSCAD-SSC), pp. 33–40 (2012)
Luo, Y., Duraiswami, R.: Canny edge detection on NVIDIA CUDA. In: IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2008. CVPRW’08, pp. 1–8 (2008)
Rao, L., Zhang, B., Zhao, J.: Hardware implementation of reconfigurable 1D convolution. J. Signal Process. Syst. 82(1), 1–16 (2016)
He, W., Yuan, K.: An improved Canny edge detector and its realization on FPGA. In: 7th World Congress on Intelligent Control and Automation, IEEE, pp. 6561–6564 (2008)
Gentsos, C., Sotiropoulou, C.L., Nikolaidis, S., Vassiliadis, N.: Real-time canny edge detection parallel implementation for FPGAs. In: 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), IEEE, pp. 499–502 (2010)
Xu, Q., Varadarajan, S., Chakrabarti, C., Karam, L.J.: A distributed canny edge detector: algorithm and FPGA implementation. IEEE Trans. Image Process. 23(7), 2944–2960 (2014)
Sangeetha, D., Deepa, P.: FPGA implementation of cost-effective robust Canny edge detection algorithm. J. Real-Time Image Process. 1–14 (2016). https://doi.org/10.1007/s11554-016-0582-2
Huang, J., Parris, M., Lee, J., Demara, R.F.: Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embed. Comput. Syst. 9(1) (2009). https://doi.org/10.1145/1596532.1596541
Ahmad, A., Amira, A., Nicholl, P., Krill, B.: FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration. J. Real-Time Image Process. 8(3), 327–340 (2013)
Lee, J., Ryu, C., Kim, S.: Self-reconfigurable approach for computation-intensive motion estimation algorithm in H.264/AVC. Opt. Eng. 51(4), 047008 (2012). https://doi.org/10.1117/1.OE.51.4.047008
Hentati, M., Aoudni, Y., Nezan, J.F., Abid, M., Déforges, O.: FPGA dynamic reconfiguration using the RVC technology: inverse quantization case study. In: Proceedings of Conference on Design and Architectures for Signal and Image Processing, IEEE, pp. 1–7 (2011)
Fons, F., Fons, M., Cantó, E., López, M.: Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications. J. Real-Time Image Process. 8(3), 229–251 (2013)
Bhandari, S., Subbaraman, S., Pujari, S., Cancare, F., Bruschi, F., Santambrogio, M.D., Grassi, P.R.: High speed dynamic partial reconfiguration for real time multimedia signal processing. In: Proceedings of 15th Euromicro Conference on Digital System Design, IEEE, pp. 319–326 (2012)
Kanopoulos, N., Vasanthavada, N., Baker, R.L.: Design of an image edge detection filter using the Sobel operator. IEEE J. Solid-State Circuits 23(2), 358–367 (1988)
Canny, J.: A computational approach to edge detection. IEEE Trans. Pattern Anal. Mach. Intell. 6, 679–698 (1986)
Xilinx.: Partial reconfiguration of a processor peripheral tutorial, pp. 1–41 (2012)
Beckhoff, C., Koch, D., Torresen, J.: Go AHEAD: a partial reconfiguration framework. In: Proceedings IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 37–44 (2012)
Xilinx.: LogiCORE IP OPB HWICAP v1.00 (2006)
Xilinx.: LogiCORE IP XPS HWICAP v5.00 (2010)
Xilinx.: LogiCORE IP AXI HWICAP v2.03 (2012)
Vipin, K., Fahmy, S.A.: A high speed open source controller for FPGA partial reconfiguration. In: 2012 International Conference on Field-Programmable Technology (FPT), IEEE, Seoul, 10–12 Dec 2012. https://doi.org/10.1109/FPT.2012.6412113
Fons, F., Fons, M., Cantó, E.: Run-time self-reconfigurable 2D convolver for adaptive image processing. Microelectron. J. 42(1), 204–217 (2011)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Orlandić, M., Svarstad, K. An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration. J Real-Time Image Proc 16, 2409–2424 (2019). https://doi.org/10.1007/s11554-018-0753-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11554-018-0753-4