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Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs

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Abstract

Modern day field programmable gate arrays have carry-chains and look-up tables as the basic logic elements. Efficient realization of different arithmetic circuits on FPGAs demands an improved mapping of different functionalities onto these logic elements. A majority of the work related to the implementation of different arithmetic circuits on FPGAs focusses on the architectural optimization that can be carried out at the top level. While this works well for ASICs, the performance on FPGAs may be degrading due to the poor mapping of the architecture onto the underlying FPGA resources. In this paper, we present technology-optimized fixed-point bit-parallel multiplier structures. The multipliers are technology-optimized by re-structuring the initial Boolean networks and transforming them into an optimized circuit net-list that utilizes the target elements efficiently. A detailed theoretical and experimental analysis of our implementation using Xilinx FPGAs shows a subsequent speed-up in performance when compared to the conventional realizations. We have also compared our implementation against various technology-independent realizations reported in prior literature. The idea is to provide a clear cut analysis about the performance speed-up that is achievable through technology-dependent approaches.

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References

  1. Compton, K., & Hauck, S. (June 2002). Reconfigurable computing: a survey of systems and software. ACM Computing Surveys, 34(2), 171–210.

    Article  Google Scholar 

  2. Tessier, R., & Burleson, W. (2002). Reconfigurable computing and digital signal processing: past, present and future. Programmable Digital Signal Processors, 147–186.

  3. Ashour, M. A., & Saleh, H. I. (2000). An FPGA implementation guide for some different types of serial-parallel multiplier structures. Microelectronics Journal, 31, 161–168.

    Article  Google Scholar 

  4. Woods, R., McAllister, J., Lightbody, G., & Yi, Y. (2008). FPGA-based implementation of signal processing systems. Wiley.

  5. Tessier, R., & Burleson, W. (2001). Reconfigurable computing for DSP: A Survey. Journal of VLSI Signal Processing, 28, 7–27.

  6. Todman, T. J., Constantinides, G. A., Wilton, S. J. E., Mencer, O., Luk, W., & Cheung, P. Y. K. (2005). Reconfigurable computing: architecture and design methods. IEEE Proceedings. Computer Digital Technology, 152(2).

  7. Naseer, R., Balakrishnan, M., & Kumar, A. (1998). Direct mapping of RTL structures onto LUT-Based FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(7).

  8. Jaiswal, M. K., & Cheung, R. C. C. (2013) Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectronics Journal, 44, 21–430.

  9. Hauck, S., & Dehon, A. (2008). Reconfigurable computing: the theory and practice of FPGA-based computing. Morgan Kaufmann series.

  10. Brown, S. D., Rose, J., Francis, R. J., & Vranesic, Z. G. (1992). Field programmable gate arrays. Kluwer Academic Publisher.

  11. Ling, A., Singh, D. P., & Brown, S. D. (2005). FPGA technology mapping: a study of optimality. IEEE Proceedings Design Automation Conference, 427–432.

  12. Chen, D., & Cong, J. (2004). DAO map: a depth-optimal area optimization mapping algorithm for FPGA designs. IEEE/ACM International Conference on Computer Aided Design.

  13. Anderson, J. H., & Wang, Q. (2011). Area-efficient fpga logic elements: architecture and synthesis, 16th Asia and South Pacific Design Automation Conference (ASP-DAC).

  14. Xilinx (2009). Virtex-5 family overview, DS100 (v 5.0) Feb. 6, 2009. www.xilinx.com.

  15. Xilinx (2010). Virtex-6 libraries guide for HDL designs, UG623 (v 12.3) September 21, 2010. www.xilinx.com.

  16. Xilinx (2011). Spartan-6 family overview, DS160 (v 2.0) October 25, 2011. www.xilinx.com.

  17. Cardarilli, G. C., Pontarelli, S., Re, M., & Salsano, A. (2008). On the use of Signed Digit Arithmetic for the new 6-Inputs LUT based FPGAs, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS.

  18. Zhou, G., Li, L., & Michalik, H. (2008). Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAs, International Conference on Field Programmable Logic and Applications, FPL.

  19. Gao, S., Khalili, D. A., & Chabbini, N. (2007). Optimized realization of large-size two’s complement multipliers on FPGAs, IEEE Northeast Workshop on Circuits and Systems, NEWCAS.

  20. Altera Corporation (2006). “Stratix III device handbook,” V.1.

  21. Xlinx DSP Design Considerations (2006). Xtreme DSP for Virtex-4 FPGAs, UG073, (v 2.2).

  22. Kuon, I., & Rose, J. (2007). Measuring the gap between FPGAs and ASICs. IEEE Transactions on CAD, 26(2), 203–215.

  23. Abedelgwad, A., & Bayoumi, M. (2007). High speed and area efficient multiply accumulate (MAC) unit for digital signal processing applications,” in Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS.

  24. Fayed, A. A., & Bayoumi, M. (2002). A merged multiplier accumulator for high speed signal processing applications, in proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

  25. Wei, G., & Ying, W. F. (2013). The implementation of FIR low-pass filter based on FPGA and DA, in Proceedings of the 4th International Conference on Intelligent Control and Information Processing, Beijing, China, 9–11 June 2013.

  26. Yuan, X., Ying, T., & Chunpeng, G. (2010). Improved design of multiplier in the digital filter. International Conference on Computer and Communication Technologies in Agriculture Engineering.

  27. Wirthlin, M. J., & McMurtrey, B. (2001). Efficient constant coefficient multiplication using advanced FPGA architectures. International Conference on Field Programmable Logic and Applications.

  28. Writhlin, M. J. (2004). Constant coefficient multiplication using look-up tables. Journal of VLSI Signal Processing, 36, 7–15.

    Article  Google Scholar 

  29. Virtex-6 FPGA Data Sheet (2010). Xilinx, Inc., San Jose, CA.

  30. Stratix-IV FPGA Family Data Sheet (2010). Altera, Corp., San Jose, CA.

  31. Parhi, K. (1999). VLSI digital signal processing systems design and implementation. Wiley.

  32. Chang, H., & Satzoda, R. K. (2010). A low error and high performance multiplexer based truncated multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 12, December 2010.

  33. Kidambi, S. S., Guibaly, F. E., & Antoniou, A. (1996). Area-efficient multiplier for digital signal processing applications. IEEE Transactions on Circuits and Systems –II: Analog & Digital Signal Processing, Vol. 43, No. 2.

  34. Stine, E., & Duverne, O. M. (2003). Variations on truncated multiplication. Proceedings of the Euromicro Symposium on Digital System Design.

  35. Baugh, R., & Wooley, B. (1973). A two’s complement parallel array multiplication algorithm. IEEE Transactions on Computers, C-22(12), 1045–1047.

  36. http://www.xilinx.com.

  37. Bhattacharjee, S., Sil, S., Basak, B., & Chakarbarti, A. (2011). Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications, International Conference on Communication and Industrial Application (ICCIA).

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  1. Department of Computer Science and Engineering, NIT, Srinagar, India

    Burhan Khurshid

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  1. Burhan Khurshid
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Correspondence to Burhan Khurshid.

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Khurshid, B. Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs. J Sign Process Syst 89, 293–317 (2017). https://doi.org/10.1007/s11265-016-1195-5

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  • DOI: https://doi.org/10.1007/s11265-016-1195-5

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