Skip to main content
SpringerLink
Log in

DBU-PG: energy-efficient noc design using dual-buffering power gating

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

With the continuous reduction in transistor size, the power consumption issue associated with the adoption of Network-on-Chips (NoCs) in multicore systems has become increasingly prominent and severe, particularly in terms of static power consumption. Currently, the techniques employed to address the issue of static power consumption in NoCs can be broadly categorized into two forms: power gating and simplified router architecture. However, these designs face critical bottlenecks in maintaining network performance stability and flexibility. In this paper, we propose a power gating approach utilizing double buffering to conserve power. Firstly, we introduce the DBU-PG router architecture, which effectively reduces network power consumption by sharing an input buffer between every two input ports when the network load is low. Secondly, through improved arbitration and flow control mechanisms, packets can be efficiently transmitted between shared buffers. Finally, we propose an improved router architecture, DBU-PG2, which enables packets in different virtual channels of the same buffer to be executed concurrently. Based on evaluation in real application, our DBU-PG and DBU-PG2 routers achieved reductions of 69% and 66%, respectively, in static power consumption compared to the baseline. Additionally, DBU-PG2 reduced packet latency by 7.5% while incurring only a 2.3% increase in area overhead.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Availability of data and materials

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

References

  1. Hoskote Y, Vangal S, Singh A, Borkar N, Borkar S (2007) A 5-ghz mesh interconnect for a teraflops processor. IEEE Micro 27(5):51–61. https://doi.org/10.1109/MM.2007.4378783

    Article  Google Scholar 

  2. Chen L, Zhu D, Pedram M, Pinkston TM (2015) Power punch: towards non-blocking power-gating of noc routers. In: 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp 378–389. https://doi.org/10.1109/HPCA.2015.7056048

  3. Yadav S, Laxmi V, Gaur MS (2020) Multiple-noc exploration and customization for energy efficient traffic distribution. In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 200–201. https://doi.org/10.1109/VLSI-SOC46417.2020.9344101

  4. Aligholipour R, Baharloo M, Farzaneh B, Abdollahi M, Khonsari A (2021) Tama: turn-aware mapping and architecture-a power-efficient network-on-chip approach. ACM Trans Embed Comput Syst 20(5). https://doi.org/10.1145/3462700

  5. Farrokhbakht H, Kamali HM, Enright Jerger N (2019) Muffin: minimally-buffered zero-delay power-gating technique in on-chip routers. In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp 1–6. https://doi.org/10.1109/ISLPED.2019.8824806

  6. Chen C, Tao Z, Miguel JS (2020) Bufferless nocs with scheduled deflection routing. In: 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp 1–6. https://doi.org/10.1109/NOCS50636.2020.9241585

  7. Huang J, Bhosekar S, Boyapati R, Wang N, Hur B, Yum KH, Kim EJ (2021) A voting approach for adaptive network-on-chip power-gating. IEEE Trans Comput 70(11):1962–1975. https://doi.org/10.1109/TC.2020.3033163

    Article  Google Scholar 

  8. Matsutani H, Koibuchi M, Ikebuchi D, Usami K, Nakamura H, Amano H (2010) Ultra fine-grained run-time power gating of on-chip routers for cmps. In: 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, pp 61–68. https://doi.org/10.1109/NOCS.2010.16

  9. Baharloo M, Aligholipour R, Abdollahi M, Khonsari A (2020) Changesub: a power efficient multiple network-on-chip architecture. Comput Electrical Eng 83:106578

    Article  Google Scholar 

  10. Chen L, Pinkston TM (2012) Nord: Node-router decoupling for effective power-gating of on-chip routers. In: 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp 270–281. https://doi.org/10.1109/MICRO.2012.33

  11. Wang P, Niknam S, Ma S, Wamg Z, Stefanov T (2019) A dynamic bypass approach to realize power efficient network-on-chip. In: 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS), pp 2019–2026. https://doi.org/10.1109/HPCC/SmartCity/DSS.2019.00279

  12. Wang P, Niknam S, Ma S, Wang Z, Stefanov T (2019) Evc-based power gating approach to achieve low-power and high performance noc. In: 2019 22nd Euromicro Conference on Digital System Design (DSD), pp 116–123. https://doi.org/10.1109/DSD.2019.00027

  13. Wang P, Niknam S, Wang Z, Stefanov T (2017) A novel approach to reduce packet latency increase caused by power gating in network-on-chip. In: 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp 1–8

  14. Das R, Narayanasamy S, Satpathy SK, Dreslinski RG (2013) Catnap: energy proportional multiple network-on-chip. In: Proceedings of the 40th Annual International Symposium on Computer Architecture

  15. Samih A, Wang R, Krishna A, Maciocco C, Tai C, Solihin Y (2013) Energy-efficient interconnect via router parking. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 508–519. https://doi.org/10.1109/HPCA.2013.6522345

  16. Farrokhbakht H, Kamali HM, Jerger NDE, Hessabi S (2018) Sponge: a scalable pivot-based on/off gating engine for reducing static power in noc routers. In: Proceedings of the International Symposium on Low Power Electronics and Design

  17. Kim G, Kim, J., Yoo, S.: Flexibuffer: Reducing leakage power in on-chip network routers. 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 936–941 (2011)

  18. Zhou W, Ouyang Y, Li J, Xu D (2022) A transparent virtual channel power gating method for on-chip network routers. Integration 88:286–297

    Article  Google Scholar 

  19. Parikh R, Das R, Bertacco V (2014) Power-aware nocs through routing and topology reconfiguration. In: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), pp 1–6

  20. Seitanidis I, Psarras A, Chrysanthou K, Nicopoulos C (2015) Elastistore: Flexible elastic buffering for virtual-channel-based networks on chip. IEEE Trans Very Large Scale Integr Syst

  21. Zhan J, Ouyang J, Ge F, Zhao J, Xie Y (2015) Dimnoc: a dim silicon approach towards power-efficient on-chip network. In: 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp 1–6

  22. Mondal HK, Harsha GNS, Kishore R, Deb S (2017) P2noc: Power- and performance-aware noc architectures for sustainable computing. Sustain Comput Informatics Syst 16:25–37

    Article  Google Scholar 

  23. Dimitrakopoulos G, Georgiadis N, Nicopoulos C, Kalligeros E Switch folding: network-on-chip routers with time-multiplexed output ports. In: 2013 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp 344–349 (2013). https://doi.org/10.7873/DATE.2013.081

  24. Tran AT, Baas BM (2014) Achieving high-performance on-chip networks with shared-buffer routers. IEEE Trans Very Large Scale Integr Syst 22(6):1391–1403

    Article  Google Scholar 

  25. Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2015) Noxim: an open, extensible and cycle-accurate network on chip simulator. In: 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp 162–163. https://doi.org/10.1109/ASAP.2015.7245728

  26. Sun C, Chen C-HO, Kurian G, Wei L, Miller J, Agarwal A, Peh L-S, Stojanovic V (2012) Dsent—a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In: 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, pp 201–210. https://doi.org/10.1109/NOCS.2012.31

  27. Hestness J, Grot B, Keckler SW (2010) Netrace: dependency-driven trace-based network-on-chip simulation. Association for Computing Machinery, New York, NY, USA. https://doi.org/10.1145/1921249.1921258

  28. Matsutani H, Koibuchi M, Amano H, Wang D (2008) Run-time power gating of on-chip routers using look-ahead routing. In: 2008 Asia and South Pacific Design Automation Conference, pp 55–60. https://doi.org/10.1109/ASPDAC.2008.4484015

  29. Hu Z, Buyuktosunoglu A, Srinivasan V, Zyuban V, Jacobson H, Bose P (2004) Microarchitectural techniques for power gating of execution units. In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758), pp 32–37. https://doi.org/10.1145/1013235.1013249

Download references

Funding

This study was funded by the National Natural Science Foundation of China (NSFC) research Projects (Grant Number 62374049).

Author information

Authors and Affiliations

  1. School of Computer Science and Information Engineering, Hefei University of Technology, Hefei, China

    Yiming Ouyang, Cheng Cao, Dongyu Xu, Wu Zhou, Zhengfeng Huang & Huaguo Liang

Authors
  1. Yiming Ouyang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Cheng Cao
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Dongyu Xu
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Wu Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Zhengfeng Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Huaguo Liang
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

YO was contributed to funding acquisition. CC was contributed to writing—original draft, methodology. DX was contributed to writing—review and editing. WZ was contributed to data curation. ZH was contributed to validation. HL was contributed to validation.

Corresponding author

Correspondence to Cheng Cao.

Ethics declarations

Conflict of interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Ethical approval

Our work does not involve human and animal research.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ouyang, Y., Cao, C., Xu, D. et al. DBU-PG: energy-efficient noc design using dual-buffering power gating. J Supercomput (2024). https://doi.org/10.1007/s11227-024-06000-4

Download citation

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s11227-024-06000-4

Keywords

Search

Navigation