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High-level power estimation techniques in embedded systems hardware: an overview

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Abstract

Power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited power budget systems (battery-operated hand-held devices, electro-optical pluggable modules, IoT and green energy systems, etc.). Subsequently, early power consumption estimation at design time is crucial for power optimization. The aim of this paper is to present an overview of high-level power estimation techniques currently available along with a comprehensive comparison between different methodologies and their applications on estimated models. When high speed and high performance are key features of a specific embedded system, increase in energy consumption becomes the main hurdle to be tackled while keeping speed/performance v/s power consumption trade-off at a minimum. This paper provides designers, interested in power consumption modeling, with knowledge on how to select best power estimation techniques applied to designated target models.

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Authors and Affiliations

  1. Univ Rennes, INSA Rennes, CNRS, IETR - UMR 6164, F-35000, Rennes, France

    Majdi Richa, Jean-Christophe Prévotet & Mickaël Dardaillon

  2. Lebanese University, FoE, CRSI, Beirut, Lebanon

    Mohamad Mroué & Abed Ellatif Samhat

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  1. Majdi Richa
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Richa, M., Prévotet, JC., Dardaillon, M. et al. High-level power estimation techniques in embedded systems hardware: an overview. J Supercomput 79, 3771–3790 (2023). https://doi.org/10.1007/s11227-022-04798-5

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