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Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits

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Abstract

Emerging non-volatile memories (NVMs) are known as promising alternatives to SRAMs in on-chip caches. However, their limited write endurance is a major challenge when NVMs are employed in these highly frequently written caches. Early wear-out of NVM cells makes the lifetime of the caches extremely insufficient for nowadays computational systems. Previous studies only addressed the lifetime of data part in the cache. This paper first demonstrates that the age bits field of the cache replacement algorithm is the most frequently written part of a cache block and its lifetime is shorter than that of data part by more than 27\(\times\). Second, it investigates the effect of age bits wear-out on the cache operation and shows that the performance is severely degraded after even a small portion of age bits become non-operational. Third, a novel cache replacement algorithm, so-called Sleepy-LRU, is proposed to reduce the write activity of the age bits with negligible overheads. The evaluations show that Sleepy-LRU extends the lifetime of instruction and data caches to 3.63\(\times\) and 3.00\(\times\), respectively, with an average of 0.06% performance overhead. In addition, Sleepy-LRU imposes no area and power consumption overhead.

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Funding

Funding was provided by Iran’s National Elites Foundation.

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Authors and Affiliations

  1. Sharif University of Technology (SUT), Tehran, Iran

    Seyedeh Golsana Ghaemi & Iman Ahmadpour

  2. Tehran University (TU), Tehran, Iran

    Mehdi Ardebili

  3. Amirkabir University of Technology, P.O. Box 15916-34311, Tehran, Iran

    Hamed Farbeh

  4. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran

    Hamed Farbeh

Authors
  1. Seyedeh Golsana Ghaemi
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  2. Iman Ahmadpour
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  3. Mehdi Ardebili
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  4. Hamed Farbeh
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Correspondence to Hamed Farbeh.

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Ghaemi, S.G., Ahmadpour, I., Ardebili, M. et al. Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits. J Supercomput 75, 3945–3974 (2019). https://doi.org/10.1007/s11227-019-02758-0

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